公开(公告)号：US20090013207A1

公开(公告)日：2009-01-08

申请号：US12189416

申请日：2008-08-11

申请人： Pradip Bose ,  Zhigang Hu ,  Jude A. Rivers ,  Jeonghee Shin ,  Victor Zyuban

发明人： Pradip Bose ,  Zhigang Hu ,  Jude A. Rivers ,  Jeonghee Shin ,  Victor Zyuban

IPC分类号： G06F11/00

CPC分类号： G06F11/008

摘要： A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.

摘要翻译： 一种预测集成电路器件相对于一个或多个故障机制的寿命可靠性的方法包括将集成电路器件分解成结构; 将每个结构分解成元素和设备; 评估每个设备以确定设备是否容易受到故障机制的影响，并消除确定不易受到攻击的设备; 对于每个确定的易受攻击的设备，估计设备故障对与其相关联的特定元件的功能的影响，以及将故障分类为致命故障或非致命故障，其中致命故障导致使用 给定设备失败; 确定对于那些故障致命的设备，有效的应力程度和/或时间; 确定设备的故障率和致命故障的概率中的一个或多个，并且在整个结构和故障机制中聚合它们。

公开(公告)号：US07325124B2

公开(公告)日：2008-01-29

申请号：US10828794

申请日：2004-04-21

申请人： Erik Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

发明人： Erik Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Victor Zyuban

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3885

摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.

摘要翻译： 管道系统和方法包括多个操作阶段。 这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。 功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

公开(公告)号：US06678795B1

公开(公告)日：2004-01-13

申请号：US09639263

申请日：2000-08-15

申请人： Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

发明人： Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

IPC分类号： G06F1208

CPC分类号： G06F12/0862 ,  G06F2212/6024

摘要： There is provided a method for fetching at least one of instructions and operand data from a second memory into a first memory of a computer system having at least one processor. The method includes the step of storing a plurality of entries in a table associated with the first memory. Each entry is associated with a memory page that includes a plurality of storage elements in the second memory, and includes information of prior access by the at least one processor to each of the plurality of storage elements. Upon a miss to the first memory from the at least one processor based upon a request, the table is searched for a given entry associated with a given page that includes a target of the request. If the given entry is found, then at least one prefetch request is generated to fetch at least one storage element included in the given page from the second memory to the first memory, based upon given information comprised in the given entry.

摘要翻译： 提供了一种用于将指令和操作数中的至少一个从第二存储器读取到具有至少一个处理器的计算机系统的第一存储器中的方法。 该方法包括将多个条目存储在与第一存储器相关联的表中的步骤。 每个条目与包括第二存储器中的多个存储元件的存储器页面相关联，并且包括至少一个处理器对多个存储元件中的每一个的先前访问的信息。 在基于请求错过从至少一个处理器到第一存储器时，搜索与包括请求的目标的给定页面相关联的给定条目的表。 如果找到给定条目，则基于给定条目中包含的给定信息，生成至少一个预取请求以从包含在给定页面中的至少一个存储元件从第二存储器提取到第一存储器。

公开(公告)号：US09390989B2

公开(公告)日：2016-07-12

申请号：US13535694

申请日：2012-06-28

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： G06F17/50 ,  H01L23/14 ,  H05K3/46 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H05K3/30 ,  H01L21/48

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.

摘要翻译： 一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的计算机程序产品。 计算机可读程序代码包括被配置为从多个客户端接收系统需求的计算机可读程序代码，从系统要求中识别公共处理结构和技术，以及将公共处理结构和技术分配给3D计算机处理中的至少一个层 芯片堆栈计划。 计算机可读程序代码还被配置用于根据系统要求识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。 计算机可读程序代码还被配置用于确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。 制造设备构成3D计算机处理芯片堆栈。

公开(公告)号：US08151092B2

公开(公告)日：2012-04-03

申请号：US11034284

申请日：2005-01-12

申请人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

发明人： Erik Richter Altman ,  Michael Karl Gschwind ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman ,  Victor V. Zyuban

IPC分类号： G06F9/30

CPC分类号： G06F9/3808 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3873

摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

摘要翻译： 在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。 精确的控制信号矢量缓存可以完成。 每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。 所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。 由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存 击中。

公开(公告)号：US08108714B2

公开(公告)日：2012-01-31

申请号：US11684775

申请日：2007-03-12

申请人： Pradip Bose ,  Jude A. Rivers ,  Victor Zyuban

发明人： Pradip Bose ,  Jude A. Rivers ,  Victor Zyuban

IPC分类号： G06F11/00

CPC分类号： G06F11/1407 ,  G06F11/1008

摘要： A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting code stage before the write-back stage that checks a value to be written by the processor for any error. The error-correcting code stage may correct any error in the value, and the pipeline may lack a recovery unit pipeline.

摘要翻译： 处理器执行期间使用的软错误恢复系统。 该系统可以包括微处理器，处理器，控制器等。 系统还可以包括用于减少处理器的循环时间的管线以及流水线内的回写阶段。 该系统还可以包括在回写阶段之前的错误校正码级，该阶段检查由处理器为任何错误写入的值。 纠错码阶段可以纠正该值中的任何错误，并且管道可能缺少恢复单元管道。

公开(公告)号：US08091050B2

公开(公告)日：2012-01-03

申请号：US12243427

申请日：2008-10-01

申请人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

发明人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

摘要翻译： 提供了对软错误的系统级别影响进行建模的机制。 提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。 通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。 在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档 设计。 基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

公开(公告)号：US07865699B2

公开(公告)日：2011-01-04

申请号：US11931815

申请日：2007-10-31

申请人： Erik R Altman ,  Michael Gschwind ,  David A. Luick ,  Daniel A. Prener ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman

发明人： Erik R Altman ,  Michael Gschwind ,  David A. Luick ,  Daniel A. Prener ,  Jude A. Rivers ,  Sumedh W. Sathaye ,  John-David Wellman

IPC分类号： G06F9/00

CPC分类号： G06F9/3816 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185

摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

摘要翻译： 本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。 计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与 一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。 计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们 扩展，还是包含代码页而不是仅存储指令字的单个部分。

公开(公告)号：US20100015732A1

公开(公告)日：2010-01-21

申请号：US12174198

申请日：2008-07-16

申请人： Pradip Bose ,  Eren Kursun ,  Jude A. Rivers ,  Victor Zyuban

发明人： Pradip Bose ,  Eren Kursun ,  Jude A. Rivers ,  Victor Zyuban

IPC分类号： H01L21/00 ,  H01L21/66

CPC分类号： H01L22/20 ,  G01R31/3172 ,  G01R31/31724 ,  G06F11/20 ,  H01L21/485 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/22 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： Base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet, which provides the same functionality as one of the at least one non-functional chiplet is designed to provide, is vertically stacked. The at least one repair semiconductor chiplet provides the functionality that the at least one non-functional chiplet is designed to provide to the base semiconductor chip. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. In case a first attempt to repair the base semiconductor chip by stacking repair semiconductor chips is unsuccessful, additional repair semiconductor chips may be subsequently stacked to fully repair the base semiconductor chip.

摘要翻译： 制造并测试了每个包括多个小芯片的基底半导体芯片。 对于具有至少一个非功能小芯片的基底半导体芯片，提供与被设计为提供的至少一个非功能小灯之一相同的功能的至少一个修复半导体小芯片是垂直堆叠的。 至少一个修复半导体芯片提供了至少一个非功能小芯片被设计成提供给基底半导体芯片的功能。 形成功能性多芯片组件，其提供与所有小芯片功能性的基础半导体芯片相同的功能。 在通过堆叠修复半导体芯片来修复基底半导体芯片的第一次尝试不成功的情况下，可以随后堆叠另外的修复半导体芯片以完全修复基底半导体芯片。

公开(公告)号：US20090144669A1

公开(公告)日：2009-06-04

申请号：US11947207

申请日：2007-11-29

申请人： Pradip Bose ,  Eren Kursun ,  Jude A. Rivers ,  Victor Zyuban

发明人： Pradip Bose ,  Eren Kursun ,  Jude A. Rivers ,  Victor Zyuban

IPC分类号： B25B11/00

CPC分类号： H01L27/11803 ,  G06F17/5045 ,  G11C29/70 ,  H01L27/105 ,  H01L28/20

摘要： A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method.

摘要翻译： 一种通过应用于电子封装的三维（3D）集成来增强半导体芯片工艺变化性和寿命可靠性的方法。 还提供了用于实施本发明的方法的装置。