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1.发明授权Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits 有权基于自适应工作负载的优化与异构电流感知基线设计相结合，以减轻集成电路中的当前传输限制公开(公告)号：US08914764B2
公开(公告)日：2014-12-16
申请号：US13526252
申请日：2012-06-18
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
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2.发明申请PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES 审中-公开使用建筑级结构技术预测微处理器的寿命可靠性公开(公告)号：US20090013207A1
公开(公告)日：2009-01-08
申请号：US12189416
申请日：2008-08-11
申请人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
发明人： Pradip Bose , Zhigang Hu , Jude A. Rivers , Jeonghee Shin , Victor Zyuban
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms.
摘要翻译： 一种预测集成电路器件相对于一个或多个故障机制的寿命可靠性的方法包括将集成电路器件分解成结构; 将每个结构分解成元素和设备; 评估每个设备以确定设备是否容易受到故障机制的影响，并消除确定不易受到攻击的设备; 对于每个确定的易受攻击的设备，估计设备故障对与其相关联的特定元件的功能的影响，以及将故障分类为致命故障或非致命故障，其中致命故障导致使用 给定设备失败; 确定对于那些故障致命的设备，有效的应力程度和/或时间; 确定设备的故障率和致命故障的概率中的一个或多个，并且在整个结构和故障机制中聚合它们。
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3.发明授权Current-aware floorplanning to overcome current delivery limitations in integrated circuits 有权电流识别布局规划，以克服集成电路中的当前传输限制公开(公告)号：US08863068B2
公开(公告)日：2014-10-14
申请号：US13526194
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
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4.发明授权Token-based current control to mitigate current delivery limitations in integrated circuits 有权基于令牌的电流控制，以减轻集成电路中的当前传输限制公开(公告)号：US08826216B2
公开(公告)日：2014-09-02
申请号：US13526153
申请日：2012-06-18
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.
摘要翻译： 一种具有固定布局的集成电路（IC）的系统和方法，所述集成电路（IC）具有一个或多个具有一个或多个电流源的块，其中所述一个或多个块来自电源。 所述方法包括动态地发布到被配置为响应于在所述块处接收的指令执行操作的块，标记的保留量; 确定每个向块的指令的发出是否该块的储备标记量超过零; 其中之一是：如果该块的令牌保留大于1，则向块发出指令，并且在发出指令之后递减一个令牌块的保留令牌量，或者阻止向块发出指令 。 在该方法中，每个块可以被初始化为具有：保留令牌量为零，令牌到期期间; 令牌生成周期和令牌生成量。
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5.发明授权Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits 有权基于自适应工作负载的优化，以减轻集成电路中的当前传输限制公开(公告)号：US08683418B2
公开(公告)日：2014-03-25
申请号：US13526230
申请日：2012-06-18
CPC分类号： H01L23/00 , G06F11/00 , G06F11/3062 , H01L23/50 , H01L25/065 , H01L2224/16145 , H01L2224/16225
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
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6.发明申请公开(公告)号：US20140082580A1
公开(公告)日：2014-03-20
申请号：US13526194
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
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7.发明申请METHOD FOR IMPLEMENTING DYNAMIC LIFETIME RELIABILITY EXTENSION FOR MICROPROCESSOR ARCHITECTURES 审中-公开实现微处理器结构动态寿命可靠性扩展的方法公开(公告)号：US20090178051A1
公开(公告)日：2009-07-09
申请号：US12118050
申请日：2008-05-09
申请人： Victor Zyuban , Jeonghee Shin
发明人： Victor Zyuban , Jeonghee Shin
IPC分类号： G06F9/50
CPC分类号： G06F9/50 , G06F11/004 , G06F11/1482 , G06F11/2025 , G06F11/2028 , G06F11/203 , G06F11/2051 , G06F12/0846 , G06F2209/5011 , G06F2209/503
摘要： A method for implementing dynamic lifetime reliability extension for microprocessor architectures having a plurality of primary resources and a secondary resource pool of one or more secondary resources includes configuring a resource operational mode controller to selectively switch of the primary and secondary resources between an operational mode and a non-operational mode, wherein the non-operational mode corresponds to a lifetime extension process; configuring a resource mapper associated with the secondary resource pool and in communication with the resource operational mode controller to map a secondary resource placed into the operational mode to a corresponding primary resource placed into the non-operational mode; and configuring a transaction decoder to receive incoming transaction requests and direct the requests to one of a primary resource in the operational mode and a secondary resource in the operational mode, the secondary resource mapped to an associated primary resource placed in the non-operational mode.
摘要翻译： 一种用于实现具有多个主要资源和一个或多个次要资源的辅助资源池的微处理器架构的动态生命周期可靠性扩展的方法包括配置资源操作模式控制器以在操作模式和操作模式之间选择性地切换主要和次要资源 非操作模式，其中所述非操作模式对应于终身延长过程; 配置与所述辅助资源池相关联并与所述资源操作模式控制器通信的资源映射器，以将放置在所述操作模式中的辅助资源映射到放置在所述非操作模式中的相应主资源; 以及配置事务解码器以接收传入的事务请求并将所述请求引导到所述操作模式中的主资源之一，以及将所述辅助资源映射到放置在所述非操作模式中的相关联的主资源。
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8.发明授权System and method for implementing dynamic lifetime reliability extension for microprocessor architectures 有权用于实现微处理器架构的动态终生可靠性扩展的系统和方法公开(公告)号：US07386851B1
公开(公告)日：2008-06-10
申请号：US11969413
申请日：2008-01-04
申请人： Victor Zyuban , Jeonghee Shin
发明人： Victor Zyuban , Jeonghee Shin
CPC分类号： G06F9/50 , G06F11/004 , G06F11/1482 , G06F11/2025 , G06F11/2028 , G06F11/203 , G06F11/2051 , G06F12/0846 , G06F2209/5011 , G06F2209/503
摘要： A system for implementing dynamic lifetime reliability extension for microprocessor architectures having a plurality of primary resources and a secondary resource pool of one or more secondary resources includes a resource operational mode controller configured to selectively switch of the primary and secondary resources between an operational mode and a non-operational mode, wherein the non-operational mode corresponds to a lifetime extension process; a resource mapper associated with the secondary resource pool and in communication with the resource operational mode controller, configured to map a secondary resource placed into the operational mode to a corresponding primary resource placed into the non-operational mode; and a transaction decoder configured to receive incoming transaction requests and direct the requests to one of a primary resource in the operational mode and a secondary resource in the operational mode, the secondary resource mapped to an associated primary resource placed in the non-operational mode.
摘要翻译： 一种用于为具有多个主要资源和一个或多个次要资源的辅助资源池的微处理器架构实现动态生命周期可靠性扩展的系统包括：资源操作模式控制器，被配置为在操作模式和操作模式之间选择性地切换主要和次要资源 非操作模式，其中所述非操作模式对应于终身延长过程; 与所述辅助资源池相关联并与所述资源操作模式控制器通信的资源映射器，被配置为将放置在所述操作模式中的次级资源映射到放置在所述非操作模式中的相应主资源; 以及交易解码器，被配置为接收进入的交易请求并将所述请求定向到所述操作模式中的主要资源之一，以及所述操作模式中的辅助资源，所述辅助资源被映射到放置在所述非操作模式中的相关联的主要资源。
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9.发明申请ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权基于自适应工作负载的优化与异构电流基准设计相结合，以减轻集成电路中的电流传输限制公开(公告)号：US20140195996A1
公开(公告)日：2014-07-10
申请号：US13526252
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
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10.发明申请Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits 有权基于令牌的电流控制，以缓解集成电路中的当前传输限制公开(公告)号：US20140082574A1
公开(公告)日：2014-03-20
申请号：US13526153
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
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