公开(公告)号：US6157205A

公开(公告)日：2000-12-05

申请号：US197856

申请日：1998-11-23

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K19/00346

Abstract: A technique for reducing jitter on a data channel utilized for transfer of data between components disposed on the channel. Instead of coupling a ground of the channel directly to a ground network of a chip containing the data transferring device, an impedance between the channel ground and a substrate is utilized to minimize the jitter.

Abstract translation: 一种用于减少用于在设置在信道上的组件之间传送数据的数据信道上的抖动的技术。 代替将信道的接地直接耦合到包含数据传输装置的芯片的地网，使用信道地与衬底之间的阻抗来最小化抖动。

公开(公告)号：US5777912A

公开(公告)日：1998-07-07

申请号：US623134

申请日：1996-03-28

Applicant: Ka Yin Leung ,  Eric J. Swanson ,  Kafai Leung

Inventor： Ka Yin Leung ,  Eric J. Swanson ,  Kafai Leung

IPC: H03H17/06 ,  G06F17/10

CPC classification number: H03H17/06

Abstract: A linear phase FIR filter includes a multiplication/accumulator engine which is operable to receive the multi-level data stream and multiply it by predetermined filter coefficients. The coefficients are symmetrical to allow a pre-addition operation wherein the data is first stored in a buffer and then the data for symmetrical coefficients added before multiplication by the coefficient. This results in a reduction of multiplications by a factor of two, thus allowing the multiplication/accumulator engine to operate at one-half the clock rate of the oversampled multi-level data bit stream. The pre-addition operation results in values of greater than "1" and less than "-1" which are then converted in the multiplication/accumulator engine to restrict the values that are input to the multiplication/accumulator engine to values of "+1", "0" and "-1", to allow the multiplication/accumulator engine to only perform a "pass through" of the coefficient value, an "inversion" of the coefficient value or replace the coefficient value with a "null" value. This is facilitated by processing the tri-level data through two paths, one for the "-1" and one for the "-1" term and providing a common mode offset in each of the paths. Additionally, the "-1" term has a correction factor associated therewith that can be added in the "-1" path prior to summing the two terms to provide a digital output at the sampling frequency.

Abstract translation: 线性相位FIR滤波器包括乘法/累加器引擎，其可操作以接收多电平数据流并将其乘以预定的滤波器系数。 系数是对称的，以允许预先加法操作，其中首先将数据存储在缓冲器中，然后将数据乘以系数之前加上的对称系数。 这导致乘法减少2倍，从而允许乘法/累加器引擎以过采样多电平数据比特流的时钟速率的一半工作。 预加法运算导致大于“1”且小于“-1”的值，然后在乘法/累加器引擎中转换，将输入乘法/累加器引擎的值限制为“+1” “，”0“和”-1“，以允许乘法/累加器引擎仅执行系数值的”通过“，系数值的”反转“或者以”零“值代替系数值 。 这通过两个路径处理三电平数据来实现，一个用于“-1”，一个用于“-1”项，并且在每个路径中提供共模偏移。 此外，“-1”项具有与之相关联的校正因子，其可以在对两个项求和之前以“-1”路径相加，以提供采样频率处的数字输出。

公开(公告)号：US5644257A

公开(公告)日：1997-07-01

申请号：US635570

申请日：1996-04-22

Applicant: Donald A. Kerth ,  Dan B. Kasha ,  Eric J. Swanson ,  Anthony G. Mellissinos

Inventor： Donald A. Kerth ,  Dan B. Kasha ,  Eric J. Swanson ,  Anthony G. Mellissinos

IPC: G06G7/14 ,  G11C27/02 ,  H03K5/24 ,  H03K5/159 ,  G06G7/10

CPC classification number: G11C27/024 ,  G06G7/14 ,  G11C27/02 ,  H03K5/2481 ,  H03K5/249

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Abstract translation: 通过使用初级和次级输入到采样电路，可以将模拟输入信号通过抗混叠滤波器到采样电路的有害非线性充电电流最小化。 辅助输入在主输入之前被接通，并且为采样电路内的寄生电容充电所需的电荷和补充前一周期中丢失的通道电荷主要通过次级输入提供。 在二次输入关闭之后，主输入端立即连接到采样节点，只有通过主输入才能将信号微调到采样电容器中所需的电荷。 因此，大多数非线性电荷注入通过二次输入，并且通过主输入的信号用于在实际采样操作期间微调采样电路内部的电压电平。

公开(公告)号：US5621339A

公开(公告)日：1997-04-15

申请号：US121244

申请日：1993-09-14

Applicant: Donald A. Kerth ,  Eric J. Swanson

Inventor： Donald A. Kerth ,  Eric J. Swanson

IPC: H03F3/45 ,  H03K5/24 ,  H03K5/22

CPC classification number: H03F3/45479 ,  H03K5/2481 ,  H03K5/249 ,  H03F2200/331

Abstract: A differential input stage for a data conversion device includes two sections, one section for operating during a high stress portion of a charge transfer operation and one portion for operating during the remainder of the charge transfer operation. The first portion is comprised of two differential transistors (84) and (86) having the sources and bodies thereof connected to a source coupled node and connected through a switch (94) to a current source (92). The drains of transistors (84) and (86) are connected through switches (110) and (112), respectively, to output terminals. During the second half of the charge transfer operation, differential transistors (78) and (88), having the sources and bodies thereof connected to a source coupled node and connected to the current source (92) through a switch (90), are rendered operable with the drains thereof connected through switches (96) and (104), respectively, to the output terminals. Only one of the differential pairs is operable at any one time. When they are not operational, the sources, bodies and drains thereof are connected together and to a flush terminal (118) through respective switches. These switches flush out trapped oxide charges and allow the charges to once again become mobile.

Abstract translation: 用于数据转换装置的差分输入级包括两个部分，一个部分用于在电荷转移操作的高应力部分期间操作，一个部分用于在剩余的电荷转移操作期间操作。 第一部分包括两个差分晶体管（84）和（86），它们的源极和本体连接到源极耦合节点，并通过开关（94）连接到电流源（92）。 晶体管（84）和（86）的漏极分别通过开关（110）和（112）连接到输出端子。 在电荷转移操作的第二半期间，具有连接到源耦合节点并且通过开关（90）连接到电流源（92）的源极和主体的差分晶体管（78）和（88）被渲染 可操作地将其通过开关（96）和（104）连接的排水口分别连接到输出端子。 差分对只有一个可以在任何一个时间工作。 当它们不可操作时，其源极，主体和下水道通过相应的开关连接在一起并连接到冲水端子（118）。 这些开关清除被捕获的氧化物电荷，并允许电荷再次移动。

公开(公告)号：US5594439A

公开(公告)日：1997-01-14

申请号：US295451

申请日：1994-08-24

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1076

Abstract: Abnormal changes in the non-linear characteristics of electronic components are an indication of abnormal conditions such as impending component or system failure. To detect such abnormal changes in nonlinearity, an electronic circuit is subjected to a calibration signal including at least one frequency component. Nonlinearity in the electronic circuit causes distortion components to be generated from the calibration signal. Preferably the nonlinearity is characterized by compensation coefficients that digitally compensate the nonlinearity. The compensation coefficients are adjusted in a feedback loop in response to measured values of the distortion components, so that the distortion components are minimized. At the end of the adjustment process, the transfer function of the electronic circuit is specified by the compensation coefficients, which are stored in memory. The compensation coefficients are compared to respective limits to detect abnormal nonlinearity, and any abnormal nonlinearity is reported to a human operator or to a diagnostic computer. At various times, the measurement process is repeated, and the new values of the compensation coefficients are again compared to their respective limits as well as to their previous values stored in memory. Changes in the compensation coefficients with respect to their previous values are computed and compared to respective "drift" limits, so that abnormal conditions are also detected from abnormal changes in the nonlinearity over intervals of time.

Abstract translation: 电子部件的非线性特性的异常变化是即将发生的部件或系统故障等异常情况的指示。 为了检测非线性的这种异常变化，电子电路经受包括至少一个频率分量的校准信号。 电子电路中的非线性导致从校准信号产生失真分量。 优选地，非线性的特征在于对数字补偿非线性的补偿系数。 响应于失真分量的测量值，在反馈回路中调整补偿系数，使得失真分量最小化。 在调整过程结束时，电子电路的传递函数由存储在存储器中的补偿系数指定。 将补偿系数与相应的极限进行比较，以检测异常非线性，并向人类操作员或诊断计算机报告任何异常非线性。 在不同时间，重复测量过程，并且将补偿系数的新值再次与它们各自的限制以及存储在存储器中的其先前值进行比较。 计算补偿系数相对于其先前值的变化，并将其与相应的“漂移”极限进行比较，从而也可以在时间间隔内的非线性异常变化中检测异常条件。

公开(公告)号：US5528239A

公开(公告)日：1996-06-18

申请号：US870599

申请日：1992-04-17

Applicant: Eric J. Swanson ,  Charles D. Thompson

Inventor： Eric J. Swanson ,  Charles D. Thompson

IPC: H03M1/08 ,  H03M3/02

CPC classification number: H03M3/348 ,  H03M3/424 ,  H03M3/458

Abstract: The output gates of a delta-sigma modulator can generate i(t) transient signal in the power supply lines of a delta-sigma modulator. These i(t) spikes, which would otherwise produce non-linearities which can be coupled into the frequency band of interest of the modulator, are made to be linear by using return-to-zero data encoding and by providing multi-bit outputs to the delta-sigma modulator in which the output states all have equal numbers of logic ones at the output lines for each of the output states.

Abstract translation: Δ-Σ调制器的输出门可以在Δ-Σ调制器的电源线中产生i（t）瞬态信号。 否则将产生可以耦合到调制器感兴趣的频带中的非线性的这些i（t）尖峰通过使用返回到零数据编码而被做成线性的，并且通过提供多位输出 其中输出状态对于每个输出状态在输出线处具有相等数量的逻辑1的Δ-Σ调制器。

公开(公告)号：US5440305A

公开(公告)日：1995-08-08

申请号：US937993

申请日：1992-08-31

Applicant: Bruce D. Signore ,  Eric J. Swanson

Inventor： Bruce D. Signore ,  Eric J. Swanson

IPC: G01R1/28 ,  G01K7/01 ,  G01K15/00 ,  G01R35/00 ,  G05F3/30 ,  G12B13/00 ,  H03F1/30 ,  H03M1/10 ,  H03M1/12

CPC classification number: G01K15/00 ,  G01K7/01 ,  G12B13/00 ,  H03M1/12 ,  G01R35/005

Abstract: A method and apparatus for calibration of errors in a monolithic reference includes a bandgap voltage reference (50) that outputs an untrimmed voltage and a temperature voltage. The untrimmed voltage and temperature voltage are input to a delta-sigma A/D converter (52) which has the output thereof processed through a digital filter (54) to output data on a data bus (58) for storage in an EEPROM (60). The EEPROM (60) is operable in one mode to store temperature history data and, in another mode, to store temperature compensation data. In one mode, temperature compensation parameters are retrieved from the EEPROM (60) and utilized by a multiplier/accumulator circuit (74) to generate compensation factors which are output as a digital word to a DAC (76) for controlling a trim circuit (14). The trim circuit (14) provides a temperature compensation for the output of the bandgap voltage reference (50). The system is operable in a calibration mode to measure temperatures during a burn-in procedure and calculate necessary information to determine compensation factors and store these in the EEPROM ( 60). This temperature data is extracted from the EEPROM (60) and output to a serial I/O port (64), compensation factors determined and then stored back in the EEPROM (60). The delta-sigma A/D converter (52) in the run mode then makes temperature measurements for use by the multiplier/accumulator circuit (74) in determining the appropriate compensation data to extract from the EEPROM (60) to trim the output of the bandgap voltage reference circuit (50).

Abstract translation: 用于校准单片参考中的误差的方法和装置包括输出未修整电压和温度电压的带隙电压基准（50）。 未经校验的电压和温度电压被输入到Δ-ΣA / D转换器（52），其具有通过数字滤波器（54）处理的输出，以在数据总线（58）上输出数据以存储在EEPROM（60 ）。 EEPROM（60）可以在一种模式下操作以存储温度历史数据，并且在另一模式下存储温度补偿数据。 在一种模式中，从EEPROM（60）检索温度补偿参数并由乘法器/累加器电路（74）利用来产生作为数字字输出的补偿系数到用于控制微调电路（14）的DAC（76） ）。 微调电路（14）为带隙电压基准（50）的输出提供温度补偿。 该系统在校准模式下可操作以在老化过程期间测量温度，并计算确定补偿因子的必要信息并将其存储在EEPROM（60）中。 该温度数据从EEPROM（60）提取并输出到串行I / O端口（64），然后确定补偿因子并将其存储回EEPROM（60）。 运行模式中的Δ-ΣA / D转换器（52）然后进行温度测量，以供乘法器/累加器电路（74）使用以确定适当的补偿数据以从EEPROM（60）提取以修剪 带隙电压参考电路（50）。

公开(公告)号：US5121080A

公开(公告)日：1992-06-09

申请号：US633478

申请日：1990-12-21

Applicant: Baker P. L. Scott, III ,  Eric J. Swanson

Inventor： Baker P. L. Scott, III ,  Eric J. Swanson

IPC: H03F1/56 ,  H03F3/45

CPC classification number: H03F1/56 ,  H03F3/45071

Abstract: An amplifier with controlled output impedance has a first output connected to the inverting input of the amplifier, and a second output, which forms the output of the amplifier, connected through a feedback conductance to the inverting input of the amplifier. A input conductance is connected from the inverting input to ground, and the input signal is connected to the positive input of the amplifier. The first and second outputs are provided by first and second current output stages. The currents provided by the first and second output stages are proportional to each other by a predetermined ratio. By proper selection of this predetermined ratio and the feedback and input conductances the desired output impedance and overall gain of the amplifier into a given load can be achieved.

Abstract translation: 具有受控输出阻抗的放大器具有连接到放大器的反相输入的第一输出，以及形成放大器的输出的第二输出，其通过反馈电导连接到放大器的反相输入端。 输入电导从反相输入端连接到地，输入信号连接到放大器的正输入端。 第一和第二输出由第一和第二电流输出级提供。 由第一和第二输出级提供的电流彼此成比例地以预定的比例。 通过适当地选择该预定比例并且反馈和输入电导可以实现将给定负载的放大器的期望输出阻抗和总体增益。

公开(公告)号：US5012244A

公开(公告)日：1991-04-30

申请号：US429214

申请日：1989-10-27

Applicant: David R. Wellard ,  Donald A. Kerth ,  Bruce P. Del Signore ,  Eric J. Swanson

Inventor： David R. Wellard ,  Donald A. Kerth ,  Bruce P. Del Signore ,  Eric J. Swanson

IPC: H03M3/02

CPC classification number: H03M3/364 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

Abstract: An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66). The output of counter (66) generates a oscillation detect signal upon detection of an oscillation, which signal is output to the control inputs of the switches (52), (54) and (56), for thirty-two cycles of the analog modulator sampling frequency. This is a sufficient amount of time to allow the loop, which is a first order loop, to zero out during the reset period.

Abstract translation: 提供了一种用于模拟调制器的振荡检测和复位电路，该模拟调制器包括具有单端差分放大器（32）的第一级积分，该单端差分放大器连接到三级后续积分（40），（42）和（44 ），在级联配置中。 最后一级积分（44）的输出端连接到一位量化器（48）的输入端。 一比特量化器（48）的输出连接到连接在求和节点（36）和负电压源之间的电流（50）反馈的输入。 求和节点（36）将电流反馈与用于输入到放大器（32）的输入电压相加。 分别在积分级（40），（42）和（44）的输入和输出两端提供开关（52），（54）和（56）。 通过振荡检测比较器（60）和（62）检测第二级积分（40）输出的不稳定状态，以启动五位计数器（66）中的计数周期。 计数器（66）的输出在检测到振荡时产生振荡检测信号，该信号在模拟调制器（52），（54）和（56）的控制输入端输出三十二个周期 采样频率。 这是足够的时间来允许在复位周期期间循环（这是第一阶循环）为零。

公开(公告)号：US4477782A

公开(公告)日：1984-10-16

申请号：US495063

申请日：1983-05-13

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03F3/343 ,  G05F3/26 ,  H03F3/30 ,  H03F3/34 ,  H03F3/345 ,  H03F3/16

CPC classification number: G05F3/262 ,  H03F3/3023 ,  H03F3/345 ,  H03F2203/30018

Abstract: Two gate-coupled pairs (12, 14; 16, 18) of MOS transistors are configured in a compound current mirror (10, 30) arrangement. Each pair includes an input (12; 16) and an output (14; 18) transistor. The output transistors are connected with their conduction paths in series between a source of output current a reference voltage node (22). Each of the input transistors is connected with its conduction path between the reference voltage node (22) and a separate current source (20, 24), with both sources supplying the same input current. One of the input transistors (12, 60) has a conduction path width-to-length ratio which is one-fourth that of the other one (16). This makes it possible to bias the output transistors with the minimum ON voltage for operation in the active region and thereby reduces power supply voltage overhead.A modified version (30) of the above arrangement includes, in addition, a transistor (32) for equalizing the drain-source voltage of the input and output transistors (16, 18) of an associated pair.An operational amplifier circuit (34) is described which is particularly adapted for the use of a compound mirror arrangement of two input transistors (54, 60), two output transistors (50, 52), and an equalizing transistor (56) in its differential input stage.

Abstract translation: MOS晶体管的两个栅极耦合对（12,14; 16,18）配置在复合电流镜（10,30）中。 每对包括输入（12; 16）和输出（14; 18）晶体管。 输出晶体管与其导通路径串联连接在输出电流源参考电压节点（22）之间。 每个输入晶体管与其参考电压节点（22）和单独的电流源（20,24）之间的传导路径连接，两个源提供相同的输入电流。 输入晶体管（12,60）中的一个具有导通路径的长宽比，其为另一个输入晶体管的四分之一（16）。 这使得可以以有效区域中的最小导通电压来偏置输出晶体管，从而降低电源电压开销。 另外，上述配置的修改版本（30）还包括用于均衡相关对的输入和输出晶体管（16,18）的漏 - 源电压的晶体管（32）。 描述了一种运算放大器电路（34），其特别适合于在其差分中使用两个输入晶体管（54,60），两个输出晶体管（50,52）和均衡晶体管（56）的复合镜布置 输入阶段