Two gate-coupled pairs (12, 14; 16, 18) of MOS transistors are configured in a compound current mirror (10, 30) arrangement. Each pair includes an input (12; 16) and an output (14; 18) transistor. The output transistors are connected with their conduction paths in series between a source of output current a reference voltage node (22). Each of the input transistors is connected with its conduction path between the reference voltage node (22) and a separate current source (20, 24), with both sources supplying the same input current. One of the input transistors (12, 60) has a conduction path width-to-length ratio which is one-fourth that of the other one (16). This makes it possible to bias the output transistors with the minimum ON voltage for operation in the active region and thereby reduces power supply voltage overhead.A modified version (30) of the above arrangement includes, in addition, a transistor (32) for equalizing the drain-source voltage of the input and output transistors (16, 18) of an associated pair.An operational amplifier circuit (34) is described which is particularly adapted for the use of a compound mirror arrangement of two input transistors (54, 60), two output transistors (50, 52), and an equalizing transistor (56) in its differential input stage.