公开(公告)号：US20220302173A1

公开(公告)日：2022-09-22

申请号：US17500748

申请日：2021-10-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Dongni LIU ,  Liang CHEN ,  Minghua XUAN ,  Haoliang ZHENG ,  Qi QI ,  Jing LIU

IPC: H01L27/12 ,  H01L25/16 ,  G09G3/32

Abstract: A driving backplane, a display panel and a display device are disclosed. The driving backplane includes: a base substrate; a plurality of pixel driving circuits located on the base substrate; an electrode located on a side of each of the pixel driving circuits facing away from the base substrate and coupled with the pixel driving circuits; and a potential wire located between the electrode and the base substrate and coupled with the pixel driving circuits. Every at least two pixel driving circuits are coupled with a same signal line through a multiplexing controller, an orthographic projection of the controller on the base substrate completely falls into a range of a corresponding micro light emitting diode bonding region, and an orthographic projection of a control wire coupled with the controller on the base substrate completely falls into a range of an orthographic projection of the potential wire on the base substrate.

公开(公告)号：US20220130335A1

公开(公告)日：2022-04-28

申请号：US17407156

申请日：2021-08-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Dongni LIU ,  Haoliang ZHENG ,  Minghua XUAN

IPC: G09G3/3258 ,  G09G3/3291

Abstract: A pixel circuit, a driving method thereof and electronic device, relates to the technical field of display configured for. The pixel circuit comprises a driving sub-circuit comprising a control terminal, a first terminal and a second terminal, the driving sub-circuit being configured to control a driving signal flowing through the first terminal and the second terminal according to a signal of the control terminal; a voltage division control sub-circuit configured to conduct voltage division on an input data signal in response to a first scanning signal to obtain a voltage division signal, and write the voltage division signal to the first terminal of the driving sub-circuit; and a compensation sub-circuit coupled to the control terminal of the driving sub-circuit and the second terminal of the driving sub-circuit, and configured to write voltage division signal passing through driving sub-circuit to control terminal of driving sub-circuit in response to first scanning signal.

公开(公告)号：US20220121072A1

公开(公告)日：2022-04-21

申请号：US17281709

申请日：2020-01-10

Applicant: BOE Technology Group Co., Ltd.

Inventor： Liang CHEN ,  Minghua XUAN ,  Dongni LIU ,  Haoliang ZHENG ,  Li XIAO ,  Zhenyu ZHANG ,  Hao CHEN ,  Ke WANG

IPC: G02F1/1362 ,  H01L27/32

Abstract: The present disclosure discloses a display panel and a display device. The display panel includes: a base substrate, including a plurality of substrate via holes located in a display area of the display panel; and a plurality of driving signal lines and a plurality of bonding terminals, respectively located on different sides of the base substrate. At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of bonding terminals through the substrate via hole(s).

公开(公告)号：US20220101780A1

公开(公告)日：2022-03-31

申请号：US17424408

申请日：2020-09-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Li XIAO ,  Minghua XUAN ,  Dongni LIU ,  Jing LIU ,  Qi QI ,  Haoliang ZHENG ,  Zhenyu ZHANG ,  Liang CHEN ,  Hao CHEN

IPC: G09G3/32

Abstract: A pixel drive circuit includes a data write sub-circuit, an input and read sub-circuit, a drive sub-circuit, and a first output control sub-circuit. The data write sub-circuit is configured to transmit data signals input from a first data voltage terminal at different times to a first node. The input and read sub-circuit is configured to: transmit a signal of a signal transmission terminal to a second node in a write period, and transmit an electrical signal of the second node to the signal transmission terminal in a threshold voltage read period. The drive sub-circuit is configured to output a drive signal. The first output control sub-circuit is configured to: be coupled to an element to be driven, and transmit the drive signal output by the drive sub-circuit to the element to be driven.

公开(公告)号：US20200273419A1

公开(公告)日：2020-08-27

申请号：US16461818

申请日：2018-11-05

Applicant: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhichong WANG ,  Haoliang ZHENG ,  Guangliang SHANG ,  Seung Woo HAN ,  Yinglong HUANG

IPC: G09G3/36

Abstract: A shift register unit and a driving method, a grid driving circuit and a display device are disclosed. A shift register unit includes an input circuit, a first reset circuit, and an output circuit. The input circuit includes an input terminal configured to perform a first control on the first control node and the first node in response to an input signal of the input terminal, and then perform a second control on the first node under the control of the level of the first node, the first node is located in a path where the input signal incurs the first control; the first reset circuit is configured to reset the first control node in response to the first reset signal; the output circuit is configured to output an output signal to an output terminal under the control of the level of the first control node.

公开(公告)号：US20190356523A1

公开(公告)日：2019-11-21

申请号：US16414478

申请日：2019-05-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lijun YUAN ,  Haoliang ZHENG ,  Guangliang SHANG ,  Xing YAO ,  Mingfu HAN

IPC: H04L27/26 ,  H03D1/22

Abstract: A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.

公开(公告)号：US20190279588A1

公开(公告)日：2019-09-12

申请号：US16066827

申请日：2017-12-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha KIM ,  Lijun YUAN ,  Zhichong WANG ,  Mingfu HAN ,  Xing YAO ,  Guangliang SHANG ,  Seung Woo HAN ,  Yun Sik IM ,  Jing LV ,  Yinglong HUANG ,  Jung Mok JUN ,  Haoliang ZHENG

IPC: G09G3/36 ,  G11C19/28

Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.

公开(公告)号：US20190027079A1

公开(公告)日：2019-01-24

申请号：US15577402

申请日：2017-05-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang SHANG ,  Xing YAO ,  Mingfu HAN ,  Seung-Woo HAN ,  Yun-Sik IM ,  Jing LV ,  Yinglong HUANG ,  Jung-Mok JUN ,  Xue DONG ,  Haoliang ZHENG ,  Lijun YUAN ,  Zhichong WANG ,  Ji Ha KIM

IPC: G09G3/20 ,  G11C19/28

Abstract: A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.

公开(公告)号：US20180108289A1

公开(公告)日：2018-04-19

申请号：US15502983

申请日：2016-05-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang ZHENG ,  Seungwoo HAN ,  Guangliang SHANG ,  Hyunsic CHOI ,  Mingfu HAN ,  Xing YAO ,  Zhichong WANG ,  Lijun YUAN

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/20 ,  G09G2300/0408 ,  G09G2300/0871 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/02 ,  G11C19/28

Abstract: The present disclosure relates to a shift register unit and driving method thereof, a gate driving circuit and a display device. The shift register unit comprises: an input module for controlling a level of a first node based on a scan pulse, an output module for controlling a scan pulse output based on the level of the first node, a reset module for resetting the first node and the scan pulse output, and a control module for generating a reset trigger signal, wherein the reset module further resets the first node based on the reset trigger signal. The shift register units can be cascaded to form a gate driving circuit to realize output of multiple scan pulses. By integrating such a gate driving circuit on the array substrate, area of the bezel region of the array substrate can be reduced, thereby facilitating bezel narrowing of a display device. At the same time, due to presence of the control module, the reset module is enabled to reset the first node more stably while normal output of the scan pulse is maintained.

公开(公告)号：US20250081609A1

公开(公告)日：2025-03-06

申请号：US18555254

申请日：2022-12-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Li XIAO ,  Haoliang ZHENG ,  Minghua XUAN ,  Jiao ZHAO ,  Yuzhen GUO ,  Xiaorong CUI ,  Chenyang ZHANG

IPC: H01L27/12 ,  G09G3/20 ,  G09G3/32 ,  H01L25/16

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. The display substrate includes a plurality of circuit units (Q), the plurality of circuit units (Q) includes at least a first circuit unit (Q1), a second circuit unit (Q2) and a third circuit unit (Q3), wherein the first circuit unit (Q1) includes at least a first drive transistor (DTFT1), the second circuit unit (Q2) includes at least a second drive transistor (DTFT2), the third circuit unit (Q3) includes at least a third drive transistor (DTFT3), the channel width of the first drive transistor (DTFT1) is larger than that of the second drive transistor (DTFT2) or the third drive transistor (DTFT3), and the channel length of the first drive transistor (DTFT1) is the same as that of the second drive transistor (DTFT2) or the third drive transistor (DTFT3).