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公开(公告)号：US12171117B2
公开(公告)日：2024-12-17
申请号：US17604931
申请日：2021-07-08
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: H10K50/86 , H01L27/12 , H10K59/121 , H10K59/131 , H10K59/35 , H10K59/38
Abstract: A display substrate and a display device are disclosed. In the display substrate, each sub-pixel includes: a conductive light-shielding structure; a buffer layer; a semiconductor layer; an interlayer insulating layer, located on a side of the semiconductor layer away from the buffer layer; and a conductive layer, located on a side of the interlayer insulating layer away from the semiconductor layer, and including a conductive structure. The conductive light-shielding structure includes a first main body portion and a first recessed portion, an average thickness of the first recessed portion is smaller than an average thickness of the first main body portion. The display substrate further includes a first contact hole, the first contact hole penetrates both the interlayer insulating layer and the buffer layer, the conductive structure is electrically connected with the first recessed portion through the first contact hole.
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公开(公告)号：US11984070B2
公开(公告)日：2024-05-14
申请号：US17255502
申请日：2019-12-13
Inventor： Chen Xu , Xueguang Hao , Yong Qiao , Xinyin Wu
IPC: G09G3/3225 , G09G3/3266 , H10K59/121
CPC classification number: G09G3/3225 , G09G3/3266 , H10K59/1213 , H10K59/1216 , G09G2300/0426 , G09G2300/043 , G09G2330/021
Abstract: The present disclosure provides a display substrate, in which power lines and compensation detection lines are alternately arranged at intervals, and two columns of pixel driving circuits extending along a second direction are arranged between any one of the power lines and one adjacent compensation detection line; and for any one of a plurality of pixel driving circuits, a power input terminal of the pixel driving circuit is electrically connected to the power line closest to the pixel driving circuit, and a compensation detection signal terminal of the pixel driving circuit is electrically connected to the compensation detection line closest to the pixel driving circuit. The present disclosure further provides a display device.
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公开(公告)号：US11937446B2
公开(公告)日：2024-03-19
申请号：US16977285
申请日：2019-10-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xinwei Gao , Kaihong Ma , Dacheng Zhang , Lang Liu , Chen Xu
IPC: H10K50/844 , H10K50/842 , H10K59/12 , H10K59/131 , H10K71/00
CPC classification number: H10K50/844 , H10K50/8426 , H10K59/131 , H10K71/00 , H10K59/1201
Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel the peripheral circuit is in the peripheral circuit region.
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公开(公告)号：US11930676B2
公开(公告)日：2024-03-12
申请号：US18052653
申请日：2022-11-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Lang Liu , Jingquan Wang , Chen Xu
IPC: H10K59/131 , G06F3/041 , H10K50/844 , H10K59/121 , H10K59/122 , H10K59/40 , H10K59/65 , H10K77/10 , G06F3/044 , H10K102/00
CPC classification number: H10K59/131 , G06F3/0412 , H10K50/844 , H10K59/121 , H10K59/122 , H10K59/40 , H10K59/65 , H10K77/111 , G06F3/0445 , G06F3/0446 , H10K2102/311
Abstract: A display panel and a display device are provided. The display panel includes a base substrate, a plurality of pixel drive circuit units, n first signal lines, a touch layer, and a light emitting element. A distance between first extending portions of two adjacent first signal lines is greater than a distance between first bending portions of the two adjacent first signal lines. An orthogonal projection overlap area between the first connecting portion and first extending portions of the n first signal lines is S1, and an orthogonal projection overlap area between the first connecting portion and first bending portions of the n first signal lines is S2. S1≥S2. A length of a first extending portion of at least one first signal line is L1, a distance between the first extending portion of at least one first signal line and the second electrode is H1, and H1≥(S1/n)/L1.
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公开(公告)号：US11545088B2
公开(公告)日：2023-01-03
申请号：US16480493
申请日：2019-01-11
Inventor： Chen Xu , Xueguang Hao , Jianbo Xian , Yong Qiao , Xinyin Wu
IPC: G09G3/30 , G09G3/3233 , H01L27/32
Abstract: A display panel and a display device are provided. The display panel includes: a substrate, a plurality of pixel units, a functional signal line, and a first conductive structure. The substrate includes a display area and a peripheral area on at least one side of the display area, the plurality of pixel units are in the display area, each pixel unit includes a light-emitting unit and a pixel circuit structure for providing a driving current to the light-emitting unit, and the light-emitting unit is an electroluminescent element. The functional signal line is connected with the pixel circuit structure of each pixel unit and provides a common voltage signal for the pixel circuit structure. The first conductive structure is connected in parallel with the functional signal line and is located at a layer different from that of the functional signal line.
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Patent Agency Ranking
公开(公告)号：US11386841B2
公开(公告)日：2022-07-12
申请号：US17278692
申请日：2020-07-30
Inventor： Pan Li , Xueguang Hao , Chen Xu
IPC: G09G3/3233
Abstract: A pixel driving circuit, an array substrate and a display device are provided. The pixel driving circuit includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer is arranged on the side of a gate layer lead away from a base substrate and is formed with a first via hole exposing the gate layer lead. The second interlayer dielectric layer is arranged on the side of the first interlayer dielectric layer away from the base substrate and is formed with a second via hole exposing the first via hole. A source drain layer lead is arranged on the side of the second interlayer dielectric layer away from the base substrate and is electrically connected to the gate layer lead through the first via hole and the second via hole.
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公开(公告)号：US11309427B2
公开(公告)日：2022-04-19
申请号：US16642638
申请日：2019-03-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhi Wang , Guangcai Yuan , Feng Guan , Chen Xu , Xueyong Wang , Jianhua Du , Chao Li , Lei Chen
IPC: H01L29/78 , H01L29/786 , H01L29/66
Abstract: The present disclosure relates to a thin film transistor and a manufacturing method thereof. The thin film transistor includes a substrate, a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially stacked on the substrate, the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion in source/drain regions of the thin film transistor and located on both sides of the first portion, the second portion and first sub-portions of the first portion adjacent to the second portion include an amorphous semiconductor material, a second sub-portion of the first portion between the first sub-portions includes a polycrystalline semiconductor material, and a second semiconductor layer located in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material.
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公开(公告)号：US11264384B2
公开(公告)日：2022-03-01
申请号：US16642723
申请日：2019-03-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhi Wang , Feng Guan , Guangcai Yuan , Chen Xu , Lei Chen
IPC: H01L27/092 , H01L21/8238 , H01L29/66 , H01L29/786
Abstract: The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.
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公开(公告)号：US11210989B2
公开(公告)日：2021-12-28
申请号：US16945110
申请日：2020-07-31
Inventor： Chen Xu , Xueguang Hao , Yong Qiao , Xinyin Wu
IPC: G09G3/32 , G09G3/20 , G09G3/3275 , G09G3/3266 , G09G3/3233 , H01L27/32
Abstract: Disclosed are an array substrate, a display panel and a display device. The display panel includes a plurality of sub-pixel regions; each of the sub-pixel regions includes a pixel driving circuit, a white electroluminescent device connected with the pixel driving circuit and a color resist layer corresponding to the sub-pixel region; the plurality of sub-pixel regions include a first-color sub-pixel region, a second-color sub-pixel region and a third-color sub-pixel region; a width-to-length ratio of a channel region of the driving transistor in the first-color sub-pixel region is greater than a width-to-length ratio of a channel region of the driving transistor in the second-color sub-pixel region, and the width-to-length ratio of the channel region of the driving transistor in the second-color sub-pixel region is greater than a width-to-length ratio of a channel region of the driving transistor in the third-color sub-pixel region.
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公开(公告)号：US20210366354A1
公开(公告)日：2021-11-25
申请号：US16622449
申请日：2019-03-18
Inventor： Xinguo Li , Chen Xu , Xinyin Wu , Yong Qiao , Xueguang Hao
IPC: G09G3/20 , G09G3/3225 , G09G3/00
Abstract: The present disclosure relates to a shift register for a display panel. The shift register may include an input terminal, an output terminal, an input unit, an output unit, a first control unit, a second control unit, and a first isolation unit. The output unit may be configured to transmit a first level or a second level to an output terminal based on levels of a first node and a second node.
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