公开(公告)号：US20150376788A1

公开(公告)日：2015-12-31

申请号：US14468665

申请日：2014-08-26

Applicant: Applied Materials, Inc.

Inventor： Jianhua ZHOU ,  Juan Carlos ROCHA-ALVAREZ ,  Yihong CHEN ,  Abhijit Basu MALLICK ,  Oscar LOPEZ ,  Ningli LIU

IPC: C23C16/455 ,  C23C16/40 ,  C23C16/46 ,  C23C16/458 ,  C23C16/505

CPC classification number: C23C16/45565 ,  C23C16/45574 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/5096 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32449

Abstract: Embodiments disclosed herein generally include an apparatus for radical-based deposition of dielectric films. The apparatus includes a processing chamber, a radical source coupled to the processing chamber, a substrate support disposed in the processing chamber, and a dual-channel showerhead disposed between the radical source and the substrate support. The dual-channel showerhead includes a plurality of tubes and an internal volume surrounding the plurality of tubes. The plurality of tubes and the internal volume are surrounded by one or more annular channels embedded in the dual-channel showerhead. The dual-channel showerhead further includes a first inlet connected to the one or more channels and a second inlet connected to the internal volume. The processing chamber may be a PECVD chamber, and the apparatus is capable of performing a cyclic process (alternating radical based CVD and PECVD).

Abstract translation: 本文公开的实施例通常包括用于基于基团的沉积电介质膜的装置。 该设备包括处理室，耦合到处理室的自由基源，设置在处理室中的基板支撑件和设置在自由基源和基板支撑件之间的双通道喷头。 双通道淋浴头包括多个管和围绕多个管的内部容积。 多个管和内部体积被嵌入在双通道喷头中的一个或多个环形通道包围。 双通道喷头还包括连接到一个或多个通道的第一入口和连接到内部容积的第二入口。 处理室可以是PECVD室，并且该装置能够执行循环过程（基于交替自由基的CVD和PECVD）。

公开(公告)号：US20150221480A1

公开(公告)日：2015-08-06

申请号：US14601274

申请日：2015-01-21

Applicant: Applied Materials, Inc.

Inventor： Ren-Guan DUAN ,  Juan Carlos ROCHA-ALVAREZ ,  Jianhua ZHOU ,  Ningli LIU ,  Yihong CHEN ,  Abhijit Basu MALLICK ,  Sudhir R. GONDHALEKAR

IPC: H01J37/32 ,  C09D1/00

CPC classification number: H01J37/32477 ,  C09D1/00 ,  C09D7/61 ,  H01J37/32467

Abstract: In one embodiment, a processing chamber is disclosed wherein at least one surface of the processing chamber has a coating comprising SivYwMgxAlyOz, wherein v ranges from about 0.0196 to 0.2951, w ranges from about 0.0131 to 0.1569, x ranges from about 0.0164 to 0.0784, y ranges from about 0.0197 to 0.1569, z ranges from about 0.5882 to 0.6557, and v+w+x+y+z=1.

Abstract translation: 在一个实施方案中，公开了一种处理室，其中处理室的至少一个表面具有包含SivYwMg x AlyO z的涂层，其中v为约0.0196至0.2951，w为约0.0131至0.1569，x为约0.0164至0.0784，y为 范围为约0.0197至0.1569，z范围为约0.5882至0.6557，v + w + x + y + z = 1。

公开(公告)号：US20150194317A1

公开(公告)日：2015-07-09

申请号：US14574928

申请日：2014-12-18

Applicant: Applied Materials, Inc.

Inventor： PRAMIT MANNA ,  Abhijit Basu MALLICK ,  Ludovic GODET ,  Yongmei CHEN ,  Jun XUE ,  Mukund SRINIVASAN ,  Ellie Y. YIEH ,  Srinivas D. NEMANI

IPC: H01L21/308 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L21/3086 ,  H01L21/31144 ,  H01L21/31155

Abstract: Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to increase the hardness and density of the hardmask. The ion implantation of the amorphous carbon hardmask also maintains or reduces the internal stress of the hardmask. The etch selective hardmask generally provides for improved patterning in advanced NAND and DRAM devices.

Abstract translation: 本文描述的实施例提供了形成蚀刻选择性硬掩模的方法。 非晶碳硬掩模被植入各种掺杂剂以增加硬掩模的硬度和密度。 无定形碳硬掩模的离子注入还保持或减少硬掩模的内部应力。 蚀刻选择性硬掩模通常提供高级NAND和DRAM器件中的改进的图案化。

公开(公告)号：US20150167160A1

公开(公告)日：2015-06-18

申请号：US14270216

申请日：2014-05-05

Applicant: Applied Materials, Inc.

Inventor： Yihong CHEN ,  Shaunak MUKHERJEE ,  Amit CHATTERJEE ,  Pramit MANNA ,  Abhijit Basu MALLICK ,  Ningli LIU ,  Jianhua ZHOU ,  Juan Carlos ROCHA-ALVAREZ ,  Mukund SRINIVASAN

IPC: C23C16/452

CPC classification number: C23C16/452 ,  H01J37/32357 ,  H01J37/32422

Abstract: One or more precursor gases, such as one or more silicon-containing gases, which may be one or more organosilicon and/or tetraalkyl orthosilicate gases, are introduced into a processing chamber and exposed to radicals. Dielectric films deposited using the techniques disclosed herein may contain silicon. The deposited films may exhibit few defects, low shrinkage, and high etch selectivity, mechanical stability, and thermal stability. The deposition conditions can be very mild, so damage to the substrate and the as-deposited films from UV radiation and ion bombardment is minimal or nonexistent.

Abstract translation: 一种或多种前体气体，例如一种或多种含硅气体，其可以是一种或多种有机硅和/或原硅酸四烷基酯，被引入处理室并暴露于自由基。 使用本文公开的技术沉积的介质膜可以含有硅。 沉积膜可能表现出很少的缺陷，低收缩率和高蚀刻选择性，机械稳定性和热稳定性。 沉积条件可能非常温和，因此对紫外辐射和离子轰击对基底和沉积膜的损伤最小或不存在。

公开(公告)号：US20150126045A1

公开(公告)日：2015-05-07

申请号：US14520721

申请日：2014-10-22

Applicant: Applied Materials, Inc.

Inventor： Amit CHATTERJEE ,  Abhijit Basu MALLICK ,  Nitin K. INGLE

IPC: H01L21/02

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/4411 ,  C23C16/452 ,  C23C16/45582 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274

Abstract: Embodiments of the present invention generally provide methods for forming a silicon nitride layer on a substrate. In one embodiment, a method of forming a silicon nitride layer using remote plasma chemical vapor deposition (CVD) at a temperature that is less than 300 degrees Celsius is disclosed. The precursors for the remote plasma CVD process include tris(dimethylamino)silane (TRIS), dichlorosilane (DCS), trisilylamine (TSA), bis-t-butylaminosilane (BTBAS), hexachlorodisilane (HCDS) or hexamethylcyclotrisilazane (HMCTZ).

Abstract translation: 本发明的实施方案通常提供在衬底上形成氮化硅层的方法。 在一个实施例中，公开了在小于300摄氏度的温度下使用远程等离子体化学气相沉积（CVD）形成氮化硅层的方法。 用于远程等离子体CVD工艺的前体包括三（二甲基氨基）硅烷（TRIS），二氯硅烷（DCS），三甲基胺（TSA），双 - 叔丁基氨基硅烷（BTBAS），六氯二硅烷（HCDS）或六甲基环三硅氮烷（HMCTZ）。

公开(公告)号：US20190027362A1

公开(公告)日：2019-01-24

申请号：US15988771

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Yi YANG ,  Yihong CHEN ,  Karthik JANAKIRAMAN ,  Abhijit Basu MALLICK

IPC: H01L21/02

Abstract: In one implementation, a method of forming an amorphous silicon layer on a substrate in a processing chamber is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate. The method further comprises forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate. The method further comprises performing a plasma treatment to the patterned features. The method further comprises depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate. The method further comprises selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer.

公开(公告)号：US20180350621A1

公开(公告)日：2018-12-06

申请号：US15995698

申请日：2018-06-01

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Shishi JIANG ,  Abhijit Basu MALLICK ,  Kurtis LESCHKIES

IPC: H01L21/311 ,  H01L21/02

Abstract: Embodiments of the disclosure generally relate to a method for dry stripping a boron carbide layer deposited on a semiconductor substrate. In one embodiment, the method includes loading the substrate with the boron carbide layer into a pressure vessel, exposing the substrate to a processing gas comprising an oxidizer at a pressure between about 500 Torr and 60 bar, heating the pressure vessel to a temperature greater than a condensation point of the processing gas and removing one or more products of a reaction between the processing gas and the boron carbide layer from the pressure vessel.

公开(公告)号：US20180350563A1

公开(公告)日：2018-12-06

申请号：US15991877

申请日：2018-05-29

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Abhijit Basu MALLICK ,  Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Sanjay KAMATH ,  Zongbin WANG ,  Hanwen ZHANG ,  Shishi JIANG

IPC: H01J37/32

Abstract: Embodiments of the disclosure generally relate to a method of processing a semiconductor substrate at a temperature less than 250 degrees Celsius. In one embodiment, the method includes loading the substrate with the deposited film into a pressure vessel, exposing the substrate to a processing gas comprising an oxidizer at a pressure greater than about 2 bars, and maintaining the pressure vessel at a temperature between a condensation point of the processing gas and about 250 degrees Celsius.

公开(公告)号：US20180337061A1

公开(公告)日：2018-11-22

申请号：US15599920

申请日：2017-05-19

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Ziqing DUAN ,  Abhijit Basu MALLICK

IPC: H01L21/32 ,  H01L21/306

Abstract: Embodiments described herein generally relate methods for selective deposition of carbon structures. In one embodiment, a method includes forming energized carbon species in a process chamber, diffusing the energized carbon species through a metal layer, wherein the metal layer is disposed on a first surface of a first material that is coplanar with a second surface of a second material, and forming a carbon structure between the first surface of the first material and the metal layer from the energized carbon species. Because the carbon structure is selectively deposited on the first surface and self-aligned to the first material, the possibility of overlay or misalignment of subsequent device layers formed on the first surface of the first material after the removal of the carbon structure is significantly reduced.

公开(公告)号：US20180218902A1

公开(公告)日：2018-08-02

申请号：US15882204

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Eswaranand VENKATASUBRAMANIAN ,  Abhijit Basu MALLICK ,  Susmit Singha ROY ,  Takehito KOSHIZAWA

IPC: H01L21/033 ,  H01L21/02 ,  C23C16/32 ,  C23C16/34 ,  C23C16/50

CPC classification number: H01L21/0332 ,  C23C16/0272 ,  C23C16/32 ,  C23C16/342 ,  C23C16/345 ,  C23C16/50 ,  C23C16/505 ,  H01L21/02175 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of hardmask films on a substrate. In one implementation, a method of forming a hardmask layer on a substrate is provided. The method comprises forming a seed layer on a substrate by supplying a seed layer gas mixture in a processing chamber. The method further includes forming a transition layer comprising tungsten, boron and carbon on the seed layer by supplying a transition layer gas mixture in the processing chamber. The method further includes forming a bulk hardmask layer comprising tungsten, boron and carbon on the transition layer by supplying a main deposition gas mixture in the processing chamber.