公开(公告)号：US07366423B2

公开(公告)日：2008-04-29

申请号：US10334839

申请日：2002-12-31

Applicant: Paul S. Levy ,  Karl H. Mauritz

Inventor： Paul S. Levy ,  Karl H. Mauritz

IPC: H04B10/00

CPC classification number: G02B6/4201 ,  G02B6/4214 ,  G02B6/4246 ,  G02B6/4274 ,  G02B6/4284

Abstract: A system includes multiple agents coupled to an optical bus for transmission of high speed signals and to an electrical bus for transmission of low speed signals. The agents can be memory modules, such as DIMMs. An optical connector housing for coupling the agent to the optical bus can include a reflective device such a mirror, a semi reflective mirror, a pellicle beamsplitter, or the like. The low speed signals can be, for example, power, ground, and supervisory signals. The high speed signals can be, for example, data, address, control, and clock signals.

Abstract translation: 系统包括耦合到光总线的多个代理，用于传输高速信号和用于传输低速信号的电总线。 代理可以是内存模块，如DIMM。 用于将试剂耦合到光学总线的光学连接器壳体可以包括反射装置，例如反射镜，半反射镜，防护薄膜分束器等。 低速信号可以是例如电源，接地和监控信号。 高速信号可以是例如数据，地址，控制和时钟信号。

公开(公告)号：US06317804B1

公开(公告)日：2001-11-13

申请号：US09201450

申请日：1998-11-30

Applicant: Paul S. Levy ,  Judson Alan Lehman

Inventor： Paul S. Levy ,  Judson Alan Lehman

IPC: G06F1300

CPC classification number: G06F13/4022

Abstract: A circuit arrangement and method interface multiple functional blocks within an integrated circuit device via a concurrent serial interconnect capable of routing separate serial command, data and clock signals between functional blocks in the device. The concurrent serial interconnect utilizes a plurality of serial ports that are selectively coupled to one another by an interface controller to define one or more logical communication channels between two or more of the serial ports. Each serial port is coupled via a point-to-point interconnection with a port interface in a functional block. In addition, the concurrent serial interconnect facilitates the design of an integrated circuit device by supporting the addition of a serial interconnect to an assemblage of functional blocks, with each functional block associated with one of a plurality of serial ports in the serial interconnect.

Abstract translation: 电路布置和方法通过能够在设备中的功能块之间路由分离的串行命令，数据和时钟信号的并行串行互连来在集成电路设备内接口多个功能块。 并发串行互连利用多个串行端口，其通过接口控制器彼此选择性地耦合以在两个或多个串行端口之间定义一个或多个逻辑通信信道。 每个串行端口通过与功能块中的端口接口的点对点互连耦合。 此外，并行串行互连通过支持将串行互连添加到功能块的组合来促进集成电路设备的设计，其中每个功能块与串行互连中的多个串行端口中的一个相关联。

公开(公告)号：US06212633B1

公开(公告)日：2001-04-03

申请号：US09105285

申请日：1998-06-26

Applicant: Paul S. Levy ,  Steve Cornelius

Inventor： Paul S. Levy ,  Steve Cornelius

IPC: H04L900

CPC classification number: H04L63/0218 ,  H04L12/40104 ,  H04L12/40117 ,  H04L12/40123 ,  H04L69/329

Abstract: A distributed firewall is utilized in conjunction with a memory-mapped serial communications interface such as that defined by the IEEE 1394 specification to permit secure data transmission between selected nodes over the interface. The distributed firewall incorporates security managers in the selected nodes that are respectively configured to control access to their associated nodes, thereby restricting access to such nodes to only authorized entities. Furthermore, encrypted transmissions may be supported to restrict unauthorized viewing of data transmitted between the selected nodes over the interface. Implementation of the distributed firewall does not modify any critical specifications for the memory-mapped communications interface that would prevent the selected nodes from residing on the same interface as other nodes that adhere to such specifications but that do not support secure data transmission.

Abstract translation: 分布式防火墙与诸如由IEEE 1394规范定义的存储器映射串行通信接口结合使用以允许通过接口在所选节点之间进行安全数据传输。 分布式防火墙将所选节点中的安全管理器合并，分别被配置为控制对其关联节点的访问，从而限制仅对授权实体访问这些节点。 此外，可以支持加密的传输以限制在接口上在所选节点之间传输的数据的未经授权的查看。 分布式防火墙的实现不会修改内存映射通信接口的任何关键规范，这将阻止所选节点与遵守这些规范但不支持安全数据传输的其他节点驻留在同一接口上。

公开(公告)号：US6041427A

公开(公告)日：2000-03-21

申请号：US958530

申请日：1997-10-27

Applicant: Paul S. Levy

Inventor： Paul S. Levy

IPC: G06F11/267 ,  G01R31/28

CPC classification number: G06F11/267 ,  Y10S370/911

Abstract: A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.

Abstract translation: 电路装置利用公共总线进行逻辑电路的功能操作，并对逻辑电路进行扫描测试。 在一个实施例中，逻辑电路的输入/输出端口和扫描测试端口可切换地耦合到总线。 为了对逻辑电路进行功能测试，通过总线发送的预定命令使得扫描测试端口被耦合到总线，并且输入/输出端口与总线分离。 然后可以经由总线向/从逻辑电路发送测试数据。 当测试完成时，通过总线发送的第二预定命令使得扫描测试端口与总线和要耦合到总线的输入/输出端口分离。

公开(公告)号：US5751151A

公开(公告)日：1998-05-12

申请号：US630685

申请日：1996-04-12

Applicant: Paul S. Levy ,  Ed Chenoweth

Inventor： Paul S. Levy ,  Ed Chenoweth

IPC: G01R31/28 ,  G01R31/02

CPC classification number: G01R31/2851

Abstract: An integrated circuit test apparatus employs a main test circuit load board which has a circular array of relay card mounts located on it. Auxiliary relays, operated in conjunction with the load board, are mounted in groups on individual relay circuit cards, each card including several relays. The relay circuit cards have connectors on first and second edges thereof; and the connectors on the first edges interconnect with the corresponding receptacles on the relay card mounts. A customized configuration board load ring for the particular integrated circuit device under test (DUT) then is placed over the second edges of the relay circuit cards to interconnect with spring-loaded connectors on these edges to effect the configuration for the operation of the particular DUT which is undergoing test at any given time.

Abstract translation: 集成电路测试装置采用具有位于其上的中继卡座的圆形阵列的主测试电路负载板。 辅助继电器与负载板一起运行，分别安装在各个继电器电路卡上，每个卡包括几个继电器。 继电器电路卡在其第一和第二边缘上具有连接器; 并且第一边缘上的连接器与继电器卡座上的相应插座相互连接。 然后将被测定的特定集成电路器件（DUT）的定制配置板负载环放置在继电器电路卡的第二边缘上，以与这些边缘上的弹簧加载连接器互连，以实现特定DUT的操作配置 在任何给定的时间正在进行测试。

公开(公告)号：US5748744A

公开(公告)日：1998-05-05

申请号：US657826

申请日：1996-06-03

Applicant: Paul S. Levy ,  Steve Cornelius

Inventor： Paul S. Levy ,  Steve Cornelius

IPC: G06F21/00 ,  H04L9/00

CPC classification number: G06F21/80

Abstract: The present invention relates to a system and method for securing sensitive data on mass storage devices. The system and method use an encryption device to encrypt sensitive data that is to be stored on the mass storage devices. A plurality of cryptographic keys are provided to ensure that only authorized personnel have the ability to access the encrypted data.

Abstract translation: 本发明涉及一种用于在大容量存储设备上确保敏感数据的系统和方法。 该系统和方法使用加密设备来加密要存储在大容量存储设备上的敏感数据。 提供了多个加密密钥以确保仅授权人员具有访问加密数据的能力。

公开(公告)号：US5659496A

公开(公告)日：1997-08-19

申请号：US581646

申请日：1995-12-28

Applicant: Paul S. Levy ,  John C. Ciccone

Inventor： Paul S. Levy ,  John C. Ciccone

IPC: G11C17/18 ,  G11C17/00

CPC classification number: G11C17/18

Abstract: The present invention relates to a system and method for programming VROM links. The system has an address selection circuit connected to the VROM link for selecting an address in the VROM link in which to program. A polarity control circuit is also connected to the VROM link. The polarity control circuit allows one to control the directional flow of a current used in programming the VROM link.

Abstract translation: 本发明涉及用于编程VROM链路的系统和方法。 该系统具有连接到VROM链路的地址选择电路，用于选择要编程的VROM链路中的地址。 极性控制电路也连接到VROM链路。 极性控制电路允许控制在VROM链路编程中使用的电流的定向流。

公开(公告)号：US5414744A

公开(公告)日：1995-05-09

申请号：US126289

申请日：1993-09-24

Applicant: Paul S. Levy

Inventor： Paul S. Levy

IPC: G11C7/10 ,  G11C19/00 ,  H03K19/0175

CPC classification number: G11C7/1093 ,  G11C19/00 ,  G11C7/1078

Abstract: A serial bit input controller uses clock and data input lines for communicating command information, as well as the clock and data information, to an integrated circuit chip. The circuit functions by employing a multi-stage shift register as a command storage register. The outputs of the shift register are connected to the inputs of coincidence logic gates, the outputs of which in turn supply signals to command state latch circuits. The selection of any one of the command state latch circuits depends upon the data stored in the multi-stage shift register. The shift register, in turn, is enabled by signals on the clock line by holding the clock line high and toggling it with data pulses. When the desired count is reached, the clock signal is allowed to resume, and is applied to the latch circuits to store the command state in the selected latch circuit. To clear the system, a two-stage binary clear latch is employed. This clear latch is enabled by signals on the clock data line when the clock signals is held low. This circuit is toggled by the next data pulse, which causes it to produce a clear output pulse to all of the command state latch circuits.

Abstract translation: 串行位输入控制器使用时钟和数据输入线将命令信息以及时钟和数据信息传送到集成电路芯片。 电路通过采用多级移位寄存器作为命令存储寄存器来起作用。 移位寄存器的输出端连接到符合逻辑门的输入端，其输出端又将信号提供给指令状态锁存电路。 命令状态锁存电路中的任何一个的选择取决于存储在多级移位寄存器中的数据。 移位寄存器又通过将时钟线保持在高电平并用数据脉冲切换来使能时钟线上的信号。 当达到期望的计数时，允许时钟信号恢复，并且被施加到锁存电路以将命令状态存储在所选择的锁存电路中。 为了清除系统，采用了两级二进制清除锁存器。 当时钟信号保持低电平时，该清除锁存器由时钟数据线上的信号使能。 该电路被下一个数据脉冲切换，这使得它向所有的指令状态锁存电路产生清除的输出脉冲。