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公开(公告)号：US10394092B2
公开(公告)日：2019-08-27
申请号：US15502992
申请日：2016-08-09
Inventor： Han Zhang , Xiaozhou Zhan
IPC: G02F1/1343 , G02F1/136 , G06F3/041 , G06F3/044 , G02F1/1333
Abstract: The present disclosure provides a display substrate and a method of manufacturing the same, and a display device. The display substrate includes a base substrate and a sensing electrode layer located on one side of the base substrate, the sensing electrode layer comprising a sensing electrode and a dummy pattern that comprises dummy sub-patterns arranged into columns, each dummy sub-pattern having a first border defining the dummy sub-pattern in a column direction, and first borders of the dummy sub-patterns being non-periodically arranged.
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公开(公告)号：US20190252487A1
公开(公告)日：2019-08-15
申请号：US16177754
申请日：2018-11-01
Inventor： Xiaowei Wang , Guoqing Zhang
IPC: H01L27/32
Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes: a voltage conducting layer, at least part of which is in a display area; a voltage connecting terminal in a peripheral circuit area, and a conductive lead in the peripheral circuit area. The conductive lead includes: a first annular portion, a second annular portion, and a plurality of bridging portions. The first annular portion is connected to the voltage conducting layer, the second annular portion surrounds the first annular portion and connected to the voltage connecting terminal, and a first end and a second end of each bridging portion are connected to the first annular portion and the second annular portion respectively. The resistance value between two ends of each bridging portion is negatively correlated to the resistance value between the second end of the bridging portion and the voltage connecting terminal.
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公开(公告)号：US20190226079A1
公开(公告)日：2019-07-25
申请号：US16213403
申请日：2018-12-07
Inventor： Jindong Liu , Chaolong Fan , Le Liu , Xiaocui Yang
Abstract: A substrate fixing carrier includes a supporting frame and a cooling plate. The supporting frame defines a hollow region and a supporting portion at an inner wall of the supporting frame. The cooling plate and the supporting frame are movable towards each other until the cooling plate is in the hollow region with edges of the cooling plate aligning with the supporting portion. When a rectangular to-be-evaporated substrate is placed in the hollow region with edges of the rectangular to-be-evaporated substrate between the supporting portion and the cooling plate, a distance between each edge of the cooling plate corresponding to each long side of the to-be-evaporated substrate and the supporting portion is greater than or equal to a thickness of the to-be-evaporated substrate, and a distance between each edge of the cooling plate corresponding to each short side of the to-be-evaporated substrate and the supporting portion is less than the thickness of the to-be-evaporated substrate.
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公开(公告)号：US10355056B2
公开(公告)日：2019-07-16
申请号：US15564084
申请日：2017-05-04
Inventor： Renrong Gai , Weilin Lai
Abstract: The present disclosure relates to an OLED device and a manufacturing method thereof, a display panel and a display device. The OLED device includes: a first electrode disposed on a substrate; an organic light emitting layer disposed on the first electrode; a second electrode disposed on the organic light emitting layer; and a stack of layers disposed on the second electrode. The stack of layers includes at least one inorganic layer and at least one organic layer. The at least one inorganic layer and at least one organic layer are alternately arranged. One organic layer of the at least one organic layer includes a color conversion layer.
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公开(公告)号：US10330849B2
公开(公告)日：2019-06-25
申请号：US15147392
申请日：2016-05-05
Inventor： Bo Wang , Zhanjie Ma , Minghua Xuan
Abstract: The present disclosure provides a quantum dot film, a method for manufacturing the same and a backlight module. The quantum dot film comprises a quantum dot layer and an optical waveguide layer, the quantum dot layer covers the optical waveguide layer, the optical waveguide layer is a laminated structure made up of a plurality of sublayers, and starting from the sublayer close to the quantum dot layer in the laminated structure, the refractive indices of sublayers become larger layer by layer. The backlight module comprises the above-mentioned quantum dot film, and the quantum dot film is located between the optical waveguide layer and the prism film.
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Patent Agency Ranking
公开(公告)号：US20190189651A1
公开(公告)日：2019-06-20
申请号：US16053460
申请日：2018-08-02
Inventor： Ke ZHAO , Guoqing ZHANG , Hongwei GAO , Xiaowei WANG , Zhihui JIA , Yan ZONG , Longfei YANG , Hongxia YANG , Meili GUO , Weifeng WANG , Pucha ZHAO , Zhixin GUO
CPC classification number: H01L27/1296 , H01L22/20 , H01L27/3244 , H01L51/56 , H01L2227/323 , H01L2251/562
Abstract: The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.
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公开(公告)号：US20190189232A1
公开(公告)日：2019-06-20
申请号：US16099513
申请日：2017-12-15
Inventor： Zhengkui Wang
CPC classification number: G11C19/287 , G09G3/20 , G09G2300/0408 , G09G2300/0426 , G09G2310/0286 , G09G2310/0297
Abstract: The present application discloses a display apparatus having a display area and a peripheral area. The display apparatus includes a gate-driver-on-array circuit in the peripheral area having N numbers of shift register units for respectively outputting a plurality of gate scanning signals to the plurality of gate lines. An n-th shift register unit of the N numbers of shift register units includes an input port for receiving an input signal from an output port of a m-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p-th shift register unit through a reset signal line, 1≤m
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438.发明申请公开(公告)号：US20190189039A1
公开(公告)日：2019-06-20
申请号：US16145396
申请日：2018-09-28
Inventor： Yishan Fu , Jun Fan , Fuqiang Li , Jiguo Wang , Yue Shan , Taiyang Liu
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0252 , G11C19/28
Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.
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公开(公告)号：US20190180706A1
公开(公告)日：2019-06-13
申请号：US16170395
申请日：2018-10-25
Inventor： Yishan Fu , Jun Fan , Fuqiang Li , Jiguo Wang
IPC: G09G3/36
Abstract: A pixel circuit and a display device are provided. The pixel circuit includes: a first inverter circuit having an input terminal connected to a first node and an output terminal connected to a second node; a second inverter circuit having an input terminal connected to the second node and an output terminal connected to a third node; a switching circuit configured to disconnect a connection between the first node and the third node when a first scanning signal is at an active level; and a control circuit configured to control a level of at least one of the first node and the second node according to a level control signal when the first scanning signal is at an active level. Based on this, it can help to avoid the output signal abnormality of the latch inside the pixel and enhance the working stability of the pixel circuit.
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公开(公告)号：US20190180662A1
公开(公告)日：2019-06-13
申请号：US16213210
申请日：2018-12-07
Inventor： Weifeng WANG , Guoqing ZHANG , Hongxia YANG , Yu FU , Xingliang WANG , Zhixin GUO , Yanbin DANG , Xiaowei WANG , Jie WU , Feiwen TIAN , Pucha ZHAO , Chenwei WANG , Xuepeng JI
CPC classification number: G09G3/006 , G09G3/3208 , H02H3/20
Abstract: The present disclosure provides a signal loading method and a signal generator. The signal loading method includes: loading a first pair of voltage signals to at least one pair of separate signal channels for a time period, respectively, wherein the first pair of voltage signals have a first voltage difference therebetween; and determining whether a short circuit occurs in the at least one pair of signal channels within the time period, and if it is determined that no short circuit occurs in the at least one pair of signal channels within the time period, loading a second pair of voltage signals having a second voltage difference therebetween to the at least one pair of signal channels at the end of the time period. The second voltage difference is greater than the first voltage difference.
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