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公开(公告)号：US20220253280A1
公开(公告)日：2022-08-11
申请号：US17557669
申请日：2021-12-21
发明人： Shaoli LIU , Shiyi ZHOU , Daofu LIU
摘要： The present disclosure provides a computing device for processing a multi-bit width value, an integrated circuit board card, a method, and a computer readable storage medium. The computing device is included in the combined processing apparatus, and the combined processing apparatus further includes a general interconnection interface, and other processing devices. The computing device interacts with the other processing device to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage device connected to an apparatus and the other processing devices and configured to store data of the apparatus and the other processing device. The solution of the present disclosure can split the multi-bit width value so that the processing capability of the processor is not influenced by the bit width.
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公开(公告)号：US11410036B2
公开(公告)日：2022-08-09
申请号：US16898493
申请日：2020-06-11
申请人： FUJITSU LIMITED
发明人： Makiko Ito
摘要： An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained based on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.
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公开(公告)号：US20220236949A1
公开(公告)日：2022-07-28
申请号：US17724253
申请日：2022-04-19
申请人： SK hynix Inc.
发明人： Choung Ki SONG
摘要： A multiplication-accumulation (MAC) includes a multiplication circuit, a pre-processing circuit, and an adder tree. The multiplication circuit performs a multiplication operation on a plurality of weight data and a plurality of vector data each having a floating-point format to output a plurality of multiplication data. The pre-processing circuit performs shifting on mantissa data of the plurality of multiplication data by a difference between first maximum exponent data having a greatest value among the exponent data of the plurality of multiplication data and the remaining exponent data to output a plurality of pre-processed mantissa data. The adder tree adds the plurality of mantissa data to output mantissa addition bits.
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公开(公告)号：US20220229782A1
公开(公告)日：2022-07-21
申请号：US17713002
申请日：2022-04-04
IPC分类号： G06F12/1045 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009
摘要： A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.
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公开(公告)号：US20220229633A1
公开(公告)日：2022-07-21
申请号：US17703744
申请日：2022-03-24
申请人： SK hynix Inc.
发明人： Choung Ki SONG
摘要： A multiplication-accumulation (MAC) includes a multiplication circuit, a pre-processing circuit, and an adder tree. The multiplication circuit performs a multiplication operation on a plurality of weight data and a plurality of vector data each having a floating-point format to output a plurality of multiplication data. The pre-processing circuit performs shifting on mantissa data of the plurality of multiplication data by a difference between first maximum exponent data having a greatest value among the exponent data of the plurality of multiplication data and the remaining exponent data to output a plurality of pre-processed mantissa data. The adder tree adds the plurality of mantissa data to output mantissa addition bits.
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公开(公告)号：US20220206802A1
公开(公告)日：2022-06-30
申请号：US17690344
申请日：2022-03-09
IPC分类号： G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.
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公开(公告)号：US20220188109A1
公开(公告)日：2022-06-16
申请号：US17686682
申请日：2022-03-04
申请人： Marvell Asia Pte Ltd
发明人： Chia-Hsin Chen , Avinash Sodani , Ulf Hanebutte , Rishan Tan , Soumya Gollamudi
摘要： A method includes receiving an input data at a floating point arithmetic operating unit, wherein the floating point operating unit is configured to perform a floating point arithmetic operation on the input data. The method includes determining whether the received input data is a qnan (quiet not-a-number) or whether the received input data is an snan (signaling not-a-number) prior to performing the floating point arithmetic operation. The method also includes converting a value of the received input data to a modified value prior to performing the floating point arithmetic operation if the received input data is either qnan or snan, wherein the converting eliminates special handling associated with the floating point arithmetic operation on the input data being either qnan or snan.
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公开(公告)号：US20220188071A1
公开(公告)日：2022-06-16
申请号：US17556389
申请日：2021-12-20
发明人： Shaoli LIU , Daofu LIU , Shiyi ZHOU
摘要： The present disclosure relates to a computing device for processing a multi-bit width value, an integrated circuit board card, a method, and a computer readable storage medium. The computing device may be included in a combined processing apparatus, and the combined processing apparatus may further include a general interconnection interface, and an other processing device. The computing device interacts with the other processing device to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage device connected to an apparatus and the other processing device and configured to store data of the apparatus and the other processing device. The solution of the present disclosure can split the multi-bit width value so that the processing capability of the processor is not influenced by the bit width.
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公开(公告)号：US20220156072A1
公开(公告)日：2022-05-19
申请号：US17588416
申请日：2022-01-31
IPC分类号： G06F9/30 , H03H17/06 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/38 , G06F9/48 , G06F17/16 , G06F7/24
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US11301805B2
公开(公告)日：2022-04-12
申请号：US16650893
申请日：2018-07-03
申请人： NEC CORPORATION
发明人： Yuuki Kubota , Takayuki Nakano
摘要： A recommended order quantity determining device 80 includes a recommended order quantity determination unit 81. The recommended order quantity determination unit 81 determines a recommended order quantity of each commodity from a required quantity of the commodity expressed by a decimal, depending on an order unit of the commodity. The recommended order quantity determination unit 81 determines the recommended order quantity of each commodity, depending on a total required quantity of a commodity category including the commodity.
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