公开(公告)号：US06975171B2

公开(公告)日：2005-12-13

申请号：US11059380

申请日：2005-02-17

申请人： Takeshi Ueno ,  Tetsuro Itakura ,  Krystyna Czarnul, legal representative

发明人： Zdzislaw Czarnul, deceased

IPC分类号： H03F3/45 ,  H03H11/04

CPC分类号： H03F3/211 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45766 ,  H03F3/45928 ,  H03F3/45991 ,  H03F2203/45138 ,  H03H11/045 ,  H03H11/32

摘要： A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

公开(公告)号：US06876070B1

公开(公告)日：2005-04-05

申请号：US09679658

申请日：2000-10-04

申请人： Moshe Gerstenhaber ,  Chau C. Tran

发明人： Moshe Gerstenhaber ,  Chau C. Tran

IPC分类号： H01L23/50 ,  H03F3/45 ,  H01L23/02 ,  H01I23/48

CPC分类号： H03F3/45475 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03F3/45991 ,  H03F2200/261 ,  H01L2924/00

摘要： A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

摘要翻译： 一种复制的集成电路芯片封装，其平衡和/或降低与增益电阻端子相关联的封装电容，以减少频率下共模抑制的劣化。

公开(公告)号：US06781464B2

公开(公告)日：2004-08-24

申请号：US10281103

申请日：2002-10-28

申请人： Takeshi Ueno ,  Tetsuro Itakura ,  Zdzislaw Czarnul

发明人： Takeshi Ueno ,  Tetsuro Itakura ,  Zdzislaw Czarnul

IPC分类号： H03F345

CPC分类号： H03F3/211 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45766 ,  H03F3/45928 ,  H03F3/45991 ,  H03F2203/45138 ,  H03H11/045 ,  H03H11/32

摘要： A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

摘要翻译： 一种平衡放大器，包括一对电压 - 电流转换器，包括第一输入端子，第二输入端子，第一输出端子和第二输出端子，用于将施加到第一输入端子的输入电压转换为从 第一输出端子和第二输出端子，其中一个转换器的第二输入端子和第二输出端子连接到另一个转换器的第二输入端子和第二输出端子，以抵消共模元件 并提取差分模式组件。

公开(公告)号：US06583658B1

公开(公告)日：2003-06-24

申请号：US10203160

申请日：2002-08-06

申请人： Otmar Kern

发明人： Otmar Kern

IPC分类号： H03H1116

CPC分类号： H03H11/32 ,  H03F3/45991 ,  H03F2200/331 ,  H03H11/1217

摘要： The invention relates to a balanced circuit arrangement for converting an asymmetric analogous input signal (S1) into a symmetrical output signal (S2, S3). A first amplifier (2) is provided, whereby the non-inverting input thereof is connected to the analogous input signal (S1) and the output signal (S2) thereof is fed back to the inverting input thereof in a negative feedback. Moreover, a second amplifier (3) is provided, whereby the non-inverting input thereof is connected to ground, the inverting input thereof is connected to the output signal (S2) of the first amplifier (2) by means of a series resistor (R2) and the output signal (S3) thereof is fed back to the inverting input thereof in a negative feedback and by means of a negative feedback resistor (R1). The negative feedback resistor (R1) and the series resistor (R2) are provided with the same resistance value. The aim of the invention is to process higher maximum levels of the source signal and to suppress noises of the second amplifier. The output signal (S3) of the second amplifier (3) is fed back to the base point of the signal source (1) for the analogous input signal (S1) in a negative feedback.

摘要翻译： 本发明涉及一种用于将不对称模拟输入信号（S1）转换为对称输出信号（S2，S3）的平衡电路装置。 提供第一放大器（2），由此其非反相输入连接到类似的输入信号（S1），并且其输出信号（S2）以负反馈反馈到其反相输入端。 此外，提供第二放大器（3），由此其非反相输入连接到地，其反相输入端通过串联电阻器（2）连接到第一放大器（2）的输出信号（S2） R2），并且其输出信号（S3）以负反馈和负反馈电阻（R1）反馈到其反相输入。 负反馈电阻（R1）和串联电阻（R2）具有相同的电阻值。 本发明的目的是处理源信号的较高最大电平并抑制第二放大器的噪声。 第二放大器（3）的输出信号（S3）在负反馈中被反馈到用于类似输入信号（S1）的信号源（1）的基点。

公开(公告)号：US20030033847A1

公开(公告)日：2003-02-20

申请号：US09932565

申请日：2001-08-13

发明人： Thomas A. Freehill ,  Timothy B. Straw

IPC分类号： G01N003/62 ,  G01N029/00

CPC分类号： G01H3/005 ,  G01N29/30 ,  G01N29/34 ,  G01N29/36 ,  G01V13/00 ,  H03F3/45991 ,  H03F2203/45048

摘要： The calibration circuit is used with a differential input, monolithic integrated circuit preamplifier in a sensor system. The calibration circuit tests the integrity of the sensor, the preamplifier, and the wiring in the sensor system. The calibration circuit includes first and second calibration capacitors having different capacitances connected to the preamplifier input leads. A calibration signal source is connected between the capacitors. The capacitors are preferably implemented on the same integrated circuit as the preamplifier. In operation, a calibration signal of known amplitude is applied to the calibration circuit and the level at the preamplifier output is determined. The level at the preamplifier output indicates certain conditions relating to the integrity of the sensor and its wiring, for example, an open circuit condition or a short circuit condition.

公开(公告)号：US06304144B1

公开(公告)日：2001-10-16

申请号：US09351403

申请日：1999-07-09

申请人： Daisuke Yamazaki ,  Seiichi Ozawa

发明人： Daisuke Yamazaki ,  Seiichi Ozawa

IPC分类号： H03F345

CPC分类号： H03F3/45991 ,  H03F3/45973

摘要： DC components are removed by a first and a second capacitor from a normal signal and its inverted signal from a first and a second input terminal, and the signals are input to a DC level generating circuit. The DC level generating circuit newly adds a DC component to the respective signals from which the DC components are removed by the first and the second capacitors, and extracts only a DC voltage from a feedback voltage with a low-pass filter using the fist and the second capacitors. The circuit of the DC level generating circuit which includes the low-pass filter using the first and the second capacitors is configured so that a high-frequency cut-off frequency other than that included into a loop gain by the low-pass filter is not included. Consequently, only one high-frequency cut-off frequency exists in the loop gain, thereby preventing a feedback circuit from oscillating.

摘要翻译： DC分量由第一和第二电容器从正常信号及其来自第一和第二输入端的反相信号中去除，并且信号被输入到DC电平发生电路。 直流电平发生电路向由第一和第二电容器除去直流分量的各个信号新添加DC分量，并且仅使用第一和第二电容器从低通滤波器的反馈电压中提取直流电压， 第二电容器。 包括使用第一和第二电容器的低通滤波器的直流电平发生电路的电路被配置为使得除了被低通滤波器包括在环路增益中的高频截止频率不是 包括。 因此，环路增益中仅存在一个高频截止频率，从而防止反馈电路振荡。

公开(公告)号：US06208482B1

公开(公告)日：2001-03-27

申请号：US09329233

申请日：1999-06-10

申请人： Yukihiro Araya ,  Takehiko Umeyama

发明人： Yukihiro Araya ,  Takehiko Umeyama

IPC分类号： G11B502

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/012 ,  G11B5/3909 ,  G11B2005/0016 ,  G11B2005/0018 ,  G11B2005/3996 ,  H03F3/45089 ,  H03F3/45475 ,  H03F3/45991 ,  H03F2203/45538 ,  H03F2203/45544 ,  H03F2203/45612 ,  H03F2203/45616

摘要： A signal amplifying circuit for an MR element in which a first terminal of a selected MR element is connected to input of an amplifier through a first resistor as well as to a second input of the amplifier through a second resistor, and a second terminal of the MR element is connected to the input of the amplifier through a capacitor. The effect of an offset voltage generated in the MR element can be suppressed to minimum with a simple configuration.

摘要翻译： 一种用于MR元件的信号放大电路，其中所选择的MR元件的第一端子通过第一电阻器连接到放大器的输入端，以及通过第二电阻器连接到放大器的第二输入端，第二端子 MR元件通过电容器连接到放大器的输入端。 通过简单的配置，可以将在MR元件中产生的偏移电压的效果抑制到最小。

公开(公告)号：US6160446A

公开(公告)日：2000-12-12

申请号：US92404

申请日：1998-06-05

申请人： Kouros Azimi ,  Dale Harvey Nelson ,  Tseng-Nan Tsai

发明人： Kouros Azimi ,  Dale Harvey Nelson ,  Tseng-Nan Tsai

IPC分类号： H03F3/45

CPC分类号： H03F3/45991 ,  H03F3/45475

摘要： An integrated circuit comprising a balanced differential amplifier. The balanced differential amplifier has a first single-ended differential amplifier coupled at a first negative differential input terminal to a first input signal through a feedback network also coupled to an output terminal of the first amplifier. The first amplifier is also coupled at a first positive differential input terminal to a second input signal through a first resistor and to a reference voltage. The balanced differential amplifier also has a second single-ended differential amplifier coupled at a second negative differential input terminal to the second input signal through a second feedback network also coupled to an output terminal of the second amplifier. The second amplifier is also coupled at a second positive differential input terminal to the first input signal through a second resistor and to the reference voltage.

摘要翻译： 一种包括平衡差分放大器的集成电路。 平衡差分放大器具有通过还耦合到第一放大器的输出端的反馈网络在第一负差分输入端耦合到第一输入信号的第一单端差分放大器。 第一放大器还通过第一电阻器和参考电压在第一正差分输入端子耦合到第二输入信号。 平衡差分放大器还具有通过还耦合到第二放大器的输出端的第二反馈网络将第二负差分输入端耦合到第二输入信号的第二单端差分放大器。 第二放大器还通过第二电阻器和参考电压在第二正差分输入端子耦合到第一输入信号。

公开(公告)号：US6133787A

公开(公告)日：2000-10-17

申请号：US306644

申请日：1999-05-06

申请人： Daniel Yerkovich ,  Douglas K. Medema ,  Randall J. Makela

发明人： Daniel Yerkovich ,  Douglas K. Medema ,  Randall J. Makela

IPC分类号： H03F1/56 ,  H03F3/45 ,  H03F1/00

CPC分类号： H03F3/45479 ,  H03F3/45991 ,  H03F2200/261

摘要： A method and apparatus for controlling the common mode impedance misbalance of an isolated single-ended circuit for all common mode paths, thereby allowing the balancing of the common mode impedances which reduces common mode effects while maintaining the advantages of the single-ended amplifier including circuit simplicity and the reference input connected to circuit ground. In one embodiment, two solid shields enclose the circuit as completely as possible with the inner shield connected to circuit ground which is also the reference for all other inputs to the circuit. A discrete capacitor is connected between the outer shield and each of the non-reference inputs. When the shield is complete, i.e., solid, almost solid with minimal holes or a fine mesh, the value of the discrete capacitor is selected to match the parasitic capacitance formed between the outer shield and the inner shield. In another embodiment, the shield may be incomplete, i.e., a grid, coarse mesh or a solid shield only enclosing a portion of the circuit; this shield is connected to the non-reference input of the circuit. In this case, the exposures of the incomplete outer shield and the electronic circuit ground plane (or inner shield) to an external noise source are matched to balance the effect of their parasitic capacitances. Also, in the case of an incomplete shield, a discrete capacitor may be connected between the outer shield and the non-reference input of the circuit to enable balancing the impedances to common mode currents.

摘要翻译： 一种用于控制用于所有共模路径的隔离单端电路的共模阻抗不平衡的方法和装置，从而允许平衡共模阻抗，其降低共模效应，同时保持包括电路的单端放大器的优点 简单性和参考输入连接到电路接地。 在一个实施例中，两个固体屏蔽件使电路尽可能完全地与连接到电路接地的内部屏蔽件封闭，该内部屏蔽件也是电路的所有其它输入的基准。 分离电容器连接在外屏蔽和每个非参考输入之间。 当屏蔽完成时，即固体，几乎固体具有最小的孔或细网格时，选择分立电容器的值以匹配在外屏蔽和内屏蔽之间形成的寄生电容。 在另一个实施例中，屏蔽可能是不完整的，即栅格，粗网或纯屏蔽仅包围电路的一部分; 该屏蔽连接到电路的非参考输入。 在这种情况下，匹配不完整的外屏蔽和电子电路接地层（或内部屏蔽）到外部噪声源的曝光以平衡其寄生电容的影响。 另外，在不完整的屏蔽的情况下，可以在外屏蔽和电路的非参考输入端之间连接分立电容器，以使阻抗平衡到共模电流。

公开(公告)号：US6121838A

公开(公告)日：2000-09-19

申请号：US221673

申请日：1998-12-23

申请人： William R. Freeman ,  Philip D. Shapiro

发明人： William R. Freeman ,  Philip D. Shapiro

IPC分类号： H03F1/30 ,  H03F3/345 ,  H03F3/45

CPC分类号： H03F1/306 ,  H03F3/3455 ,  H03F3/45381 ,  H03F3/45766 ,  H03F3/45991 ,  H03F2203/45542 ,  H03F2203/45702

摘要： A precision GaAs low-voltage DC amplifier includes a level shift circuit, an amplifier and a first and a second bias control circuit. The level shift circuit shifts an input signal to generate a level shifted input signal, whose bias level is controlled by a first bias control voltage. The amplifier amplifies the level shifted input signal to generate an output signal. The bias level of the output signal is controlled by a second bias control voltage. The first bias control circuit insures that the first bias control voltage varies as necessary with temperature to hold constant the bias level of the level shifted input signal. The second bias control circuit insures that the second bias control voltage varies as necessary with temperature to hold constant the bias level of the output signal.

摘要翻译： 精密GaAs低压DC放大器包括电平移位电路，放大器以及第一和第二偏置控制电路。 电平移位电路移位输入信号以产生电平移位输入信号，其偏置电平由第一偏置控制电压控制。 放大器放大电平移位输入信号以产生输出信号。 输出信号的偏置电平由第二偏置控制电压控制。 第一偏置控制电路确保第一偏置控制电压随着温度而变化，以保持电平移位输入信号的偏置电平恒定。 第二偏置控制电路确保第二偏压控制电压随温度而变化，以保持输出信号的偏置电平恒定。