公开(公告)号：US08582628B2

公开(公告)日：2013-11-12

申请号：US13148856

申请日：2010-10-20

申请人： Seiichi Ozawa ,  Hironobu Akita

发明人： Seiichi Ozawa ,  Hironobu Akita

IPC分类号： H04B1/38

CPC分类号： H04L7/10 ,  G09G3/2096 ,  G09G3/3611 ,  G09G2370/08 ,  G09G2370/14 ,  H04L7/0008 ,  H04L7/0091 ,  H04L7/0337

摘要： A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.

摘要翻译： 接收装置20n的数据接收单元21从发送装置10的数据发送单元11接收校准数据以检测接收装置20n中的数据接收状态或时钟接收状态。解码器单元24使发送单元26 发送通过将校准数据采样获得的采样器单元23的校准样本数据发送到发送设备10.发送设备10的控制单元15基于校准样本来检测接收设备20n中的数据接收状态或时钟接收状态 从接收装置20n接收到的数据，并根据检测结果控制数据发送部11和时钟发送部12。

公开(公告)号：US08553828B2

公开(公告)日：2013-10-08

申请号：US13386552

申请日：2010-07-14

申请人： Seiichi Ozawa ,  Shuhei Yamamoto

发明人： Seiichi Ozawa ,  Shuhei Yamamoto

IPC分类号： H04L25/00

CPC分类号： H04L7/033 ,  H03L7/0891

摘要： A clock data restoration device (1A) includes a sampler portion (11), a phase comparison portion (12), a drive portion (13), a charge pump (14), a capacitive element (15), a potential adjustment portion (16) and a voltage control oscillator (17). The phase comparison portion (12) outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion (13) increases or decreases a value δ to or from a variable Δ when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable Δ when the value of the variable Δ is equal to or more than +N or when the value of the variable Δ is equal to or less than −N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (14). The potential adjustment portion (16) increases or decreases a potential at a first end of a capacitive element (15) based on the signals (UP) and (DN).

摘要翻译： 时钟数据恢复装置（1A）包括取样器部分（11），相位比较部分（12），驱动部分（13），电荷泵（14），电容元件（15），电位调节部分 16）和电压控制振荡器（17）。 相位比较部分（12）输出当时钟相位（CKX）相对于输入数字信号延迟时变为有效值的信号（UP），并输出当该输入数字信号成为有效值时的信号（DN），当信号 阶段进展。 当信号（UP）和（DN）变为有效值时，驱动部分（13）增加或减小与变量Delta的值或从变量Delta增加值，并且当变量Delta的值 变量Delta等于或大于+ N，或当变量Delta的值等于或小于-N时，信号（UPFRQ）和（DNFRQ）被输出到电荷泵（14）。 电位调整部（16）基于信号（UP）和（DN）增大或减小电容元件（15）的第一端的电位。

公开(公告)号：US08331513B2

公开(公告)日：2012-12-11

申请号：US12594916

申请日：2008-10-28

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H04L7/00 ,  H04L25/00

CPC分类号： H04L7/033 ,  H04L7/0083 ,  H04L7/0087 ,  H04L25/03012

摘要： A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.

摘要翻译： 基于输入的数字信号恢复时钟信号和数据的时钟数据恢复装置1包括均衡器10，采样器20，时钟发生器30，均衡器控制器40和相位监视器50.时钟 通过采样器20和时钟发生器30的环路处理产生基于输入数字信号而恢复的时钟信号的信号CK或CKX。均衡器10的数字信号的高频分量的电平调整量为 通过均衡器10，采样器20和均衡器控制器40的环路处理进行控制。

公开(公告)号：US20120306845A1

公开(公告)日：2012-12-06

申请号：US13517462

申请日：2010-12-13

申请人： Seiichi Ozawa ,  Hironobu Akita

发明人： Seiichi Ozawa ,  Hironobu Akita

IPC分类号： G09G5/00 ,  H04L25/02

CPC分类号： G09G3/20 ,  G09G3/3611 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2370/08 ,  H04L25/0264

摘要： Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.

摘要翻译： 接收装置201〜20N依次排列成一维。 接收装置20n具有数据输入缓冲器21，第一时钟输入缓冲器221和第一时钟输出缓冲器231.第一时钟输入缓冲器221缓冲输入到第一时钟端子P21和P22的时钟，并将其输出到 第一时钟输出缓冲器231缓冲从第一时钟输入缓冲器221输入的时钟并将其从第二时钟端子P31和P32输出。 数据输入端子P11和P12位于第一时钟端子和第二时钟端子之间。

公开(公告)号：US20120068995A1

公开(公告)日：2012-03-22

申请号：US13265083

申请日：2010-04-22

申请人： Seiichi Ozawa ,  Hironobu Akita

发明人： Seiichi Ozawa ,  Hironobu Akita

IPC分类号： G06F3/038 ,  H04L7/00 ,  H04B15/00 ,  H04L25/03 ,  H04L27/06

CPC分类号： H04L7/0008 ,  G09G3/3611 ,  G09G2310/08 ,  G09G2370/08 ,  H04L7/0091 ,  H04N5/12 ,  H04N5/66

摘要： The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection section 25 of a reception apparatus 20n, based on data output from a sampler section 23, both or either of detection of a phase difference between data received by a data reception section 21 and a clock received by a clock reception section 22, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection section 25 is transmitted to a transmission apparatus 10 by a detection signal transmission section 26. In the transmission apparatus 10, by a control section 15, based on the detection signal received by a detection signal reception section 14, both or either of control of adjustment of a phase between data transmitted by a data transmission section 11 and a clock transmitted by a clock transmission section 12, and/or adjustment of an amplitude of the data is performed.

摘要翻译： 本发明提供一种易于通过接收装置中的时钟对数据进行正确采样的发送装置和接收装置。 在接收装置20n的检测部25中，根据从取样部23输出的数据，检测由数据接收部21接收到的数据与时钟接收部22接收的时钟之间的相位差， 和/或该数据的波形失真。 表示检测部25的检测结果的检测信号由检测信号发送部26发送到发送装置10.在发送装置10中，通过控制部15，基于由检测信号 接收部14，执行由数据发送部11发送的数据与时钟发送部12发送的时钟之间的相位的调整的控制和/或数据的振幅的调整。

公开(公告)号：US20110317747A1

公开(公告)日：2011-12-29

申请号：US13148856

申请日：2010-10-20

申请人： Seiichi Ozawa ,  Hironobu Akita

发明人： Seiichi Ozawa ,  Hironobu Akita

IPC分类号： H04B1/38

CPC分类号： H04L7/10 ,  G09G3/2096 ,  G09G3/3611 ,  G09G2370/08 ,  G09G2370/14 ,  H04L7/0008 ,  H04L7/0091 ,  H04L7/0337

摘要： A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.

摘要翻译： 接收装置20n的数据接收单元21从发送装置10的数据发送单元11接收校准数据以检测接收装置20n中的数据接收状态或时钟接收状态。解码器单元24使发送单元26 发送通过将校准数据采样获得的采样器单元23的校准样本数据发送到发送设备10.发送设备10的控制单元15基于校准样本来检测接收设备20n中的数据接收状态或时钟接收状态 从接收装置20n接收到的数据，并根据检测结果控制数据发送部11和时钟发送部12。

公开(公告)号：US07043202B2

公开(公告)日：2006-05-09

申请号：US10537472

申请日：2003-12-08

申请人： Seiichi Ozawa ,  Junichi Okamura

发明人： Seiichi Ozawa ,  Junichi Okamura

IPC分类号： H04B7/165 ,  H04B1/00

CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03L7/0996 ,  H03L7/18

摘要： A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.

公开(公告)号：US20060025094A1

公开(公告)日：2006-02-02

申请号：US10537472

申请日：2003-12-08

申请人： Seiichi Ozawa ,  Junichi Okamura

发明人： Seiichi Ozawa ,  Junichi Okamura

IPC分类号： H04B1/16 ,  H04B1/06 ,  H04B7/00

CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03L7/0996 ,  H03L7/18

摘要： A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.

摘要翻译： 一种相位选择型频率调制器，能够缓和对调制时钟信号的相位范围的限制。 相位选择型频率调制器包括用于产生N相时钟信号的多相时钟信号发生电路101; 控制电路104，用于顺序地激活指示从N相时钟信号中选择的时钟信号的第一组时钟选择信号中的一个; 边缘出现时间调整电路103，用于调整从控制电路104输出的第一组时钟选择信号的上升沿出现时间和/或后沿出现时间，以输出第二组时钟选择信号; 以及调制时钟信号发生电路102，用于根据从边缘出现时间调整电路103输出的第二组时钟选择信号的激活状态从N相时钟信号中选择一个时钟信号，以输出调制时钟信号MCK 。

公开(公告)号：US08363771B2

公开(公告)日：2013-01-29

申请号：US12808598

申请日：2009-10-27

申请人： Hironobu Akita ,  Seiichi Ozawa ,  Yohei Ishizone ,  Satoshi Miura

发明人： Hironobu Akita ,  Seiichi Ozawa ,  Yohei Ishizone ,  Satoshi Miura

IPC分类号： H04L7/04

CPC分类号： H04L7/10 ,  G09G5/008 ,  H03L7/095 ,  H04L7/033 ,  H04L7/046

摘要： Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

摘要翻译： 提供具有简单配置并能够可靠地执行改变的比特率的确认的传输设备，接收设备和通信系统。 通信系统1向发送装置3发送串行数据信号Sdata，该串行数据信号Sdata在传输中的串行数据信号Sdata的比特率时，在时钟周期的恒定倍数的周期内被设置为恒定值 设备2更改。 接收到串行数据信号Sdata的接收装置3当确定串行数据信号Sdata在时钟的周期的恒定倍数的周期内是恒定值时，从发送装置2接收训练数据Tdata，并且进行 以确认改变的比特率的处理。

公开(公告)号：US20120020438A1

公开(公告)日：2012-01-26

申请号：US13263679

申请日：2010-04-12

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H04L27/06

CPC分类号： H04L7/0338

摘要： A reception apparatus is an apparatus for receiving serial data and includes a sampler portion, an edge detection portion, a logical addition operation portion, a timing determination portion, a register portion, a selector portion and a latch portion. The edge detection portion inputs data OSD[n] output from the sampler portion, performs an exclusive OR operation between the data OSD[n] and data OSD[n+1] which are adjacent to each other, and outputs data EDG[n] which is the result of the exclusive OR operation. The logical addition operation portion inputs the data EDG[n] output from the edge detection portion, performs, for a predetermined time period, an OR operation on the data EDG[n], with no used as a reference value, with respect to each n which leaves a remainder of m when a difference (n−no) is divided by a value M, and outputs data EDGFLG[m] which is the result of the OR operation.

摘要翻译： 接收装置是用于接收串行数据的装置，包括采样器部分，边缘检测部分，逻辑加法运算部分，定时确定部分，寄存器部分，选择部分和锁存部分。 边缘检测部分输入从采样器部分输出的数据OSD [n]，执行彼此相邻的数据OSD [n]和数据OSD [n + 1]之间的异或运算，并输出数据EDG [n] 这是异或运算的结果。 逻辑加法运算部输入从边缘检测部输出的数据EDG [n]，对于每一个，对于数据EDG [n]执行与运算不同的参考值的预定时间的“或”运算 当差值（n-no）除以值M时剩下m的余数，并输出作为OR运算结果的数据EDGFLG [m]。