公开(公告)号：US07352250B2

公开(公告)日：2008-04-01

申请号：US11341615

申请日：2006-01-30

申请人： Yukinori Akamine ,  Manabu Kawabe ,  Satoshi Tanaka ,  Yasuo Shima ,  Ryoichi Takano

发明人： Yukinori Akamine ,  Manabu Kawabe ,  Satoshi Tanaka ,  Yasuo Shima ,  Ryoichi Takano

IPC分类号： H03L7/07 ,  H03L7/085

CPC分类号： H03L7/0895 ,  H03C3/0933 ,  H03C3/0966 ,  H03C3/0983 ,  H03C3/0991 ,  H03L7/0898 ,  H03L7/107 ,  H03L7/185

摘要： A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.

摘要翻译： 配有环路增益检测电路的PLL电路，可以抑制环路增益的变化。 当检测到环路增益时，首先改变到相位检测器的第二输入（IN-2）的输入信号的频率，并且通过电压锁定振荡器的输出来检测对应于该变化的响应。 通过将电压锁定振荡器的输出与计数器连接并将计数器的输出与积分器连接来进行检测。 通过对电荷泵电流值的检测结果执行反馈来优化锁相环特性。

公开(公告)号：US07352249B2

公开(公告)日：2008-04-01

申请号：US10679023

申请日：2003-10-03

申请人： Edmund J. Balboni ,  Wyn T. Palmer ,  Jonathan R. Strange

发明人： Edmund J. Balboni ,  Wyn T. Palmer ,  Jonathan R. Strange

IPC分类号： H03L7/085

CPC分类号： H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03J3/00 ,  H03L7/0805 ,  H03L7/0893 ,  H03L7/0898 ,  H03L7/093 ,  H04L2027/0081

摘要： A phase-locked loop frequency synthesizer has a charge pump, phase-locked loop filter, voltage-controlled oscillator, and a bandwidth calibration circuit. The bandwidth calibration circuit measures the gain of the voltage-controlled oscillator and uses the measured voltage-controlled oscillator gain to adjust the charge pump level. The charge pump level is adjusted so that a product of the voltage-controlled oscillator gain and the measured charge pump level results in a constant phase-locked loop bandwidth.

摘要翻译： 锁相环频率合成器具有电荷泵，锁相环滤波器，压控振荡器和带宽校准电路。 带宽校准电路测量压控振荡器的增益，并使用测量的压控振荡器增益来调节电荷泵电平。 调整电荷泵电平，使得压控振荡器增益和测量的电荷泵电平的乘积导致恒定的锁相环带宽。

公开(公告)号：US07333789B2

公开(公告)日：2008-02-19

申请号：US10529539

申请日：2004-08-04

申请人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

发明人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

IPC分类号： H04B1/18

CPC分类号： H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

摘要： A broadband modulation PLL includes a PLL portion containing a voltage controlled oscillator (101), a frequency divider (105), a phase comparator (104) and a loop filter (103). A frequency-dividing ratio of the frequency divider (105) is controlled to apply modulation, and also an input voltage of the voltage controlled oscillator (101) is controlled to apply modulation. One of phase modulation data for controlling the frequency dividing ratio and phase modulation data for input voltage of the voltage controlled oscillator (101) is inverted in phase by using an inverter (113), and the delay control circuit (110) detects a timing error on the basis of a signal (133) achieved by adding the output signals (131) and (132) of the filter (106) and the loop filter (103), and the timing is controlled by the delay circuits (111) and (112) to correct, the timing error.

摘要翻译： 宽带调制PLL包括包含压控振荡器（101），分频器（105），相位比较器（104）和环路滤波器（103）的PLL部分。 控制分频器（105）的分频比来施加调制，并且控制压控振荡器（101）的输入电压以进行调制。 用于控制压控振荡器（101）的输入电压的分频比和相位调制数据的相位调制数据之一通过使用逆变器（113）而相位反相，延迟控制电路（110）检测定时误差 基于通过将滤波器（106）和环路滤波器（103）的输出信号（131）和（132）相加而获得的信号（133），并且由延迟电路（111）和（ 112）纠正，定时错误。

公开(公告)号：US07333582B2

公开(公告)日：2008-02-19

申请号：US11066561

申请日：2005-02-28

申请人： Hiroyuki Yoshikawa ,  Shunsuke Hirano ,  Tatsuto Oka

发明人： Hiroyuki Yoshikawa ,  Shunsuke Hirano ,  Tatsuto Oka

IPC分类号： H03D3/24 ,  H04L27/00

CPC分类号： H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

摘要： A two-point frequency modulation apparatus is provided that reduces input timing difference and improves modulation accuracy. Two-point frequency modulation apparatus 10 has: PLL circuit 11; frequency division ratio generator 13 that generates the frequency division ratio in frequency divider 111 based on first digital baseband signal S1 and carrier signal; adder 114 that adds second digital baseband signal S2 to the output signal of loop filter 113; a delay index calculator (filter coefficient calculator 17) that calculates the delay index based on the magnitude of change in the amplitude of the output signal of adder 114; and a delay adjuster (digital filter 18) that shifts the phase of one of first digital baseband signal S1 and second digital baseband signal S2 according to the delay index so as to reduce the phase difference.

摘要翻译： 提供一种降低输入定时差并提高调制精度的两点式调频装置。 两点式调频装置10具有：PLL电路11; 分频比发生器13，其基于第一数字基带信号S1和载波信号产生分频器111中的分频比; 加法器114，其将第二数字基带信号S2添加到环路滤波器113的输出信号; 延迟指数计算器（滤波器系数计算器17），其基于加法器114的输出信号的振幅的变化幅度来计算延迟指数; 以及延迟调整器（数字滤波器18），其根据延迟指数偏移第一数字基带信号S1和第二数字基带信号S2之一的相位，以便减小相位差。

公开(公告)号：US20080030281A1

公开(公告)日：2008-02-07

申请号：US11865729

申请日：2007-10-02

申请人： Yukinori Akamine ,  Manabu Kawabe ,  Satoshi Tanaka ,  Yasuo Shima ,  Ryoichi Takano

发明人： Yukinori Akamine ,  Manabu Kawabe ,  Satoshi Tanaka ,  Yasuo Shima ,  Ryoichi Takano

IPC分类号： H03L7/085 ,  H03L7/07

CPC分类号： H03L7/0895 ,  H03C3/0933 ,  H03C3/0966 ,  H03C3/0983 ,  H03C3/0991 ,  H03L7/0898 ,  H03L7/107 ,  H03L7/185

摘要： A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.

摘要翻译： 配有环路增益检测电路的PLL电路，可以抑制环路增益的变化。 当检测到环路增益时，首先改变到相位检测器的第二输入（IN-2）的输入信号的频率，并且通过电压锁定振荡器的输出来检测对应于该变化的响应。 通过将电压锁定振荡器的输出与计数器连接并将计数器的输出与积分器连接来进行检测。 通过对电荷泵电流值的检测结果执行反馈来优化锁相环特性。

公开(公告)号：US20080007365A1

公开(公告)日：2008-01-10

申请号：US11454192

申请日：2006-06-15

申请人： Jeff Venuti ,  Jose Bohorquez

发明人： Jeff Venuti ,  Jose Bohorquez

IPC分类号： H03B5/12

CPC分类号： H03C3/0925 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/1976

摘要： A frequency synthesizer capable of high speed, low power, wideband operation including a method of gain compensation, and a method of fast voltage controlled oscillator (VCO) band calibration. In addition, the frequency synthesizer may include two or more switchable independent loop filters to facilitate wideband operation. Such a frequency synthesizer may be used in many applications, and in one example, may be particularly suitable for use in a multi-band, multi-standard transmitter or radio transceiver.

摘要翻译： 一种能够进行高速，低功率，宽带操作的频率合成器，包括增益补偿方法，以及快速压控振荡器（VCO）频带校准方法。 此外，频率合成器可以包括两个或更多个可切换的独立环路滤波器以便于宽带操作。 这种频率合成器可以用于许多应用中，并且在一个示例中，可以特别适用于在多频带，多标准发射机或无线电收发机中使用。

公开(公告)号：US20070252654A1

公开(公告)日：2007-11-01

申请号：US11785028

申请日：2007-04-13

申请人： Sascha Beyer ,  Rolf Jaehne

发明人： Sascha Beyer ,  Rolf Jaehne

IPC分类号： H03L7/00

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958

摘要： A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N≧2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a switchable frequency divider for deriving a frequency-divided signal, and b) a modulation unit that is designed to provide, at a first output, values of a divisor that are a function of the modulation signal, and at a second output, a second control voltage that is a function of the modulation signal, c) wherein the oscillator has a first control input connected to the loop filter and has a second control input connected to the second output of the modulation unit, and is designed to generate the output signal as a function of the first control voltage and the second control voltage, d) and wherein the frequency divider is connected to the first output of the modulation unit and is designed to derive the frequency-divided signal in such a manner that it has instantaneous frequencies that are a function of the divisor values. According to the invention, the modulation unit has a capacitive voltage divider with a center tap and is designed to provide the second control voltage at the center tap. The invention further concerns a transmitting/receiving device and an integrated circuit having such a frequency modulator.

摘要翻译： 提供了一种频率调制器，用于产生具有调制信号的函数的频率的输出信号，其中调制信号可以采用N≥2个不同的离散调制值，并且输出信号的预定频率值与每个调制信号相关联 调制值，包括：a）具有用于提供第一控制电压的环路滤波器的闭合锁相环，具有用于产生输出信号的压控振荡器，以及用于导出分频信号的可切换分频器，b ）调制单元，其被设计为在第一输出处提供作为调制信号的函数的除数的值，并且在第二输出处提供作为调制信号的函数的第二控制电压，c）其中 所述振荡器具有连接到所述环路滤波器的第一控制输入端，并且具有连接到所述调制单元的第二输出的第二控制输入，并且被设计成产生所述输出 信号作为第一控制电压和第二控制电压的函数，d）并且其中分频器连接到调制单元的第一输出，并且被设计为导出分频信号，使得其具有瞬时 频率是除数值的函数。 根据本发明，调制单元具有带中心抽头的电容分压器，并被设计成在中心抽头提供第二控制电压。 本发明还涉及一种具有这种频率调制器的发射/接收装置和集成电路。

公开(公告)号：US20070161360A1

公开(公告)日：2007-07-12

申请号：US11727217

申请日：2007-03-26

申请人： Toshiya Uozumi ,  Yasuyuki Kimura ,  Hirotaka Osawa ,  Satoru Yamamoto ,  Robert Henshaw

发明人： Toshiya Uozumi ,  Yasuyuki Kimura ,  Hirotaka Osawa ,  Satoru Yamamoto ,  Robert Henshaw

IPC分类号： H04B7/00

CPC分类号： H04B1/04 ,  H03C3/0925 ,  H03C3/0933 ,  H03D7/165 ,  H03D2200/0047 ,  H03J1/005 ,  H03L7/1976

摘要： In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.

摘要翻译： 在使用偏移PLL结构并且包括产生中频信号的振荡电路和分频器电路的通信半导体集成电路器件中，振荡器电路包括振荡器，可编程分频器，其根据频率分频振荡信号 信息，检测可编程分频器的输出信号和参考信号之间的相位差的相位比较器，以及用于输出指示相位差并控制振荡器的振荡频率的信号的频率控制单元，其中分频 基于与使用频带和模式信息相关的频带信息以及频道信息生成整数部分I和分数部分F / G，并产生分频比信息，从而将其分配给可编程分频器。

公开(公告)号：US20070036238A1

公开(公告)日：2007-02-15

申请号：US11204759

申请日：2005-08-15

申请人： Jorma Matero ,  Niall Shakeshaft

发明人： Jorma Matero ,  Niall Shakeshaft

IPC分类号： H04L25/03

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0991 ,  H04L27/148 ,  H04L27/152

摘要： A radio frequency modulator based on direct frequency/phase modulation of output signal of a controllable oscillator (724) that is a part of a phase locked loop (PLL) provides a direct modulator that is able to operate over a wide frequency range with a flat frequency response. A modulation signal is digitally processed (721, 730) before injection to a high-pass path of a direct modulator. Applicability of digital signal processing is based on the fact that the modulation signal is a base band signal. Therefore, the modulation signal (702) occupies such a band in the frequency domain so that a sufficient ratio of a sampling rate to an upper edge frequency of the modulation signal can be achieved. Digital processing is used for compensating an effect of non-flat high-pass PLL transfer function and/or to perform pre-distortion of the input signal of a controlled oscillator to compensate an effect of non-linearity of a controlled oscillator.

摘要翻译： 基于作为锁相环（PLL）的一部分的可控振荡器（724）的输出信号的直接频率/相位调制器的射频调制器提供能够在宽频率范围内工作的直接调制器 频率响应。 在注入直接调制器的高通路径之前，将调制信号数字处理（721,730）。 数字信号处理的适用性基于调制信号是基带信号的事实。 因此，调制信号（702）在频域中占据这样的频带，从而可以获得足够的采样率与调制信号的上边缘频率的比率。 数字处理用于补偿非平坦高通PLL传递函数的影响和/或执行受控振荡器的输入信号的预失真，以补偿受控振荡器的非线性的影响。

公开(公告)号：US20070013447A1

公开(公告)日：2007-01-18

申请号：US11410293

申请日：2006-04-25

申请人： Shunsuke Hirano ,  Hisashi Adachi

发明人： Shunsuke Hirano ,  Hisashi Adachi

IPC分类号： H03L7/00

CPC分类号： H04L27/20 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

摘要： There provides a two-point modulation phase modulation apparatus capable of obtaining an RF phase modulation signal of superior modulation precision with low power consumption and a simple configuration even in the event of inputting a wide band baseband modulation signal. A differentiator (21) of the opposite characteristics to the attenuation characteristics of anti-alias filter (22) is provided at the front stage of a D/A converter (6). As a result, it is possible to sufficiently suppress an alias signal without raising the sampling frequency of the D/A converter (6) (i.e. low power consumption) using an anti-alias filter (22) of a simple configuration (i.e. low cost) with a low order for a narrower bandwidth than a PLL modulation frequency bandwidth, and it is possible to obtain an RF phase modulation signal where the entire frequency band of input digital baseband modulation signal (S1) is reflected in a superior manner.

摘要翻译： 提供了即使在输入宽带基带调制信号的情况下，也能够获得具有低功耗的优良调制精度的RF相位调制信号和简单的配置的两点调制相位调制装置。 在D / A转换器（6）的前级设置有与抗混叠滤波器（22）的衰减特性相反特性的微分器（21）。 结果，可以使用简单配置的抗混叠滤波器（22）来充分抑制混叠信号而不提高D / A转换器（6）的采样频率（即，低功耗）（即，低成本 ）具有比PLL调制频率带宽更窄的带宽的低阶，并且可以获得输入数字基带调制信号（S1）的整个频带以优异的方式反映的RF相位调制信号。