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US07352250B2 Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems 有权
锁相环电路，偏移PLL发射机，射频集成电路和手机系统

Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems
摘要：
A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
摘要（中）：

配有环路增益检测电路的PLL电路，可以抑制环路增益的变化。 当检测到环路增益时，首先改变到相位检测器的第二输入（IN-2）的输入信号的频率，并且通过电压锁定振荡器的输出来检测对应于该变化的响应。 通过将电压锁定振荡器的输出与计数器连接并将计数器的输出与积分器连接来进行检测。 通过对电荷泵电流值的检测结果执行反馈来优化锁相环特性。

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