公开(公告)号：US20090172486A1

公开(公告)日：2009-07-02

申请号：US12400664

申请日：2009-03-09

Applicant: Don E. Ross ,  Xiaogang Du ,  Wu-Tung Cheng ,  Joseph C. Rayhawk

Inventor： Don E. Ross ,  Xiaogang Du ,  Wu-Tung Cheng ,  Joseph C. Rayhawk

IPC: G01R31/3187 ,  G06F11/00

CPC classification number: G11C29/1201 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/0405 ,  G11C2029/3202

Abstract: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.

Abstract translation: 公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。 所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。 该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。 本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。 在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。 在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

公开(公告)号：US07475300B2

公开(公告)日：2009-01-06

申请号：US11480455

申请日：2006-07-05

Applicant: Hisashi Yamauchi

Inventor： Hisashi Yamauchi

IPC: G11C29/00

CPC classification number: G01R31/318544 ,  G11C29/32 ,  G11C2029/3202

Abstract: A test method sets a write value to a scan flip-flop for setting a value to a memory to be tested. It then performs a series of shift operation in scan paths until setting of a read value is completed. During the shift operation, a value for refresh operation is added to the value passing through the flip-flop for setting a value to the memory to be tested.

Abstract translation: 测试方法将扫描触发器的写入值设置为要测试的存储器的值。 然后在扫描路径中执行一系列移位操作，直到读取值的设置完成。 在移位操作期间，将刷新操作的值添加到通过触发器的值，以将值设置到要测试的存储器。

公开(公告)号：US20080288838A1

公开(公告)日：2008-11-20

申请号：US12120538

申请日：2008-05-14

Applicant: Kenichi Anzou

Inventor： Kenichi Anzou

IPC: G01R31/28

CPC classification number: G11C29/32 ,  G11C5/04 ,  G11C2029/3202 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, an electrical package includes: an external input portion; an external output portion; a plurality of integrated circuits that is compatible with a compressed deterministic pattern test, each of the integrated circuits including: an input portion; a decompressor that is connected to the input portion; scan chains that are connected to the decompressor; a compactor that is connected to the scan chains; a selector that is connected to the compactor and the input portion to selectively output an output of the compactor or an output of the input portion; and an output portion that is connected to the selector.

Abstract translation: 根据一个实施例，电气包装包括：外部输入部分; 外部输出部分; 多个与压缩确定性模式测试兼容的集成电路，每个集成电路包括：输入部分; 连接到输入部分的解压缩器; 连接到解压缩器的扫描链; 连接到扫描链的压实机; 选择器，连接到压实机和输入部分，以选择性地输出压实机的输出或输入部分的输出; 以及连接到选择器的输出部分。

公开(公告)号：US07451370B2

公开(公告)日：2008-11-11

申请号：US11759560

申请日：2007-06-07

Applicant: Lee D. Whetsel

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/318533 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594 ,  G11C29/006 ,  G11C29/022 ,  G11C29/48 ,  G11C2029/3202

Abstract: Peripheral input and output buffer circuitry is tested using scan path circuitry selectively connecting external signals TSA, TSB, and TSC to the buffer circuitry. This is in addition to testing the internal circuitry of the integrated circuit with the scan path circuitry. An external signal, TSC, provides a load to the output of the buffer circuitry. An external signal, TSA, receives a response from input buffer circuitry and supplies a stimulus signal to output buffer circuitry. An external signal, TSB, receives a response signal from output buffer circuitry and supplies a stimulus signal to input buffer circuitry. This avoids a wafer tester having to contact bond pads connected to the buffer circuitry.

Abstract translation: 使用将外部信号TSA，TSB和TSC选择性地连接到缓冲电路的扫描路径电路测试外围输入和输出缓冲器电路。 这是除了利用扫描路径电路测试集成电路的内部电路之外的。 外部信号TSC为缓冲电路的输出提供负载。 外部信号TSA接收来自输入缓冲器电路的响应，并向输出缓冲器电路提供刺激信号。 外部信号TSB从输出缓冲器电路接收响应信号，并向输入缓冲器电路提供刺激信号。 这避免了晶片测试器必须接触连接到缓冲电路的接合焊盘。

公开(公告)号：US20080256405A1

公开(公告)日：2008-10-16

申请号：US12143007

申请日：2008-06-20

Applicant: Steven M. Eustis ,  James A. Monzel ,  Steven F. Oakland ,  Michael R. Ouellette

Inventor： Steven M. Eustis ,  James A. Monzel ,  Steven F. Oakland ,  Michael R. Ouellette

IPC: G01R31/3185 ,  G06F11/25 ,  G01R31/3187

CPC classification number: G11C29/48 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.

Abstract translation: 实现被配置为支持多个测试方法的可编译存储器结构的方法包括配置第一多个多路复用器，用于选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应内部存储器连接之间的至少一个地址路径。 第二多路复用器被配置为选择性地耦合功能存储器阵列连接和存储器逻辑连接之间的测试锁存器的输入，存储器逻辑连接耦合到至少一个数据输入路径，测试锁存器的输出定义数据 客户连接。 冲洗逻辑被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，以便于观察客户芯片上的存储器逻辑连接。

公开(公告)号：US07430695B2

公开(公告)日：2008-09-30

申请号：US11320984

申请日：2005-12-30

Applicant: Tomohiro Tanaka

Inventor： Tomohiro Tanaka

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G01R31/318536 ,  G01R31/318544 ,  G01R31/318552 ,  G11C29/48 ,  G11C2029/3202

Abstract: A register file device has a memory array, a scan connection configuration circuit, a file writing unit, a file reading unit, and a scan control circuit. The memory includes first storage devices which are obtained by adding shift transfer gate and an output gate to a master flip-flop only latch in a conventional register file using master flip-flop only latch storage devices, and a scan connection configuration circuit and a scan control circuit using master flip-flop only second storage devices are added thereto to realize the scan function of internally constituting a shift register and reading contents thereof in testing. The size of the register file is reduced by using master flip-flop only latch storage devices, and a high test/diagnosis efficiency is achieved by using the internal scan function in master-slave type flip-flop (2 latches) storage devices.

Abstract translation: 寄存器文件装置具有存储器阵列，扫描连接配置电路，文件写入单元，文件读取单元和扫描控制电路。 该存储器包括第一存储器件，其通过使用仅使用主触发器的锁存存储器件将移位传输门和输出门添加到仅在主触发器中的锁存器中获得，该锁存器仅使用主触发器，以及扫描连接配置电路和扫描 使用主触发器的控制电路仅添加第二存储装置，以实现内部组成移位寄存器的扫描功能并在其测试中读取其内容。 通过使用主触发器仅锁存存储器件来减小寄存器文件的大小，并且通过在主从型触发器（2个锁存器）存储设备中使用内部扫描功能来实现高测试/诊断效率。

公开(公告)号：US07426663B2

公开(公告)日：2008-09-16

申请号：US11785213

申请日：2007-04-16

Applicant: Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

Inventor： Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

IPC: G11C29/26 ,  G11C29/40

CPC classification number: G11C29/26 ,  G11C2029/1806 ,  G11C2029/2602 ,  G11C2029/3202

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract translation: 提供了多个桥接电路，其将来自连接到不同访问数据宽度的多个存储器的公共测试总线的测试数据信息和地址解码逻辑转换为每个存储器的固有访问数据宽度，并且还将测试地址信息 从公共测试总线到每个存储器的固有位格式，将结果提供给相应的存储器。 测试地址信息从公共测试总线并行提供给多个存储器以实现并行测试。 因此，测试数据信息可以并行地提供给不同数据宽度的多个存储器，并且用于测试地址信息的各个存储器中的地址扫描方向可以根据固有位格式被均匀化到特定方向。 因此，可以提高通过用于多个片上存储器的匹配模式的存储器测试效率。

公开(公告)号：US20080104466A1

公开(公告)日：2008-05-01

申请号：US11963689

申请日：2007-12-21

Applicant: Sankaran Menon ,  Luis Basto ,  Tien Dinh ,  Thomas Tomazin ,  Juan Revilla

Inventor： Sankaran Menon ,  Luis Basto ,  Tien Dinh ,  Thomas Tomazin ,  Juan Revilla

IPC: G01R31/28

CPC classification number: G11C29/48 ,  G01R31/318508 ,  G01R31/318513 ,  G01R31/318541 ,  G01R31/318555 ,  G11C2029/0401 ,  G11C2029/3202

Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.

Abstract translation: 嵌入式核心（例如核心终端）的输入可能不直接连接到SoC上的引脚。 直接访问嵌入式核心终端的可能会使嵌入式核心的测试复杂化。 可以使用包括边界扫描测试（BST）单元的测试包装器来测试嵌入式核心。 双功能BST / ATPG（自动测试模式生成）单元可用于对嵌入式核心执行BST和ATPG测试。 可以使用支持“通过/失败”模式的“恢复”模式的BIST（内置自测）控制器来补偿由嵌入式存储器阵列中的流水线分级引入的定时延迟。

公开(公告)号：US07342816B2

公开(公告)日：2008-03-11

申请号：US11459994

申请日：2006-07-26

Applicant: Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

Inventor： Gerald Keith Bartley ,  Darryl John Becker ,  Paul Eric Dahlen ,  Philip Raymond Germann ,  Andrew Benson Maki ,  Mark Owen Maxson

IPC: G11C5/06 ,  G11C7/10

CPC classification number: G11C29/32 ,  G11C5/04 ,  G11C8/12 ,  G11C29/26 ,  G11C2029/3202

Abstract: A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip respondent to the address/command word. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. Read data is read from the array or is received from a second data bus port for subsequent re-driving on the first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port.

Abstract translation: 适用于存储芯片的菊花链的存储芯片。 存储器芯片在第一输入端接收地址/命令字，确定地址命令字是否被引导到存储器芯片; 如果是这样，则存储器芯片访问对地址/命令字应答的存储器芯片上的阵列。 如果不是，则存储器芯片在第一输出上重新驱动地址/命令字。 作为地址/命令字的一部分或从第一数据总线端口接收写入数据。 从阵列中读取数据或从第二数据总线端口接收数据，以便随后在第一数据总线端口重新驱动。 接收总线时钟并用于接收和发送关于第一输入，第一输出，第一数据总线端口和第二数据总线端口的信息。

公开(公告)号：US20080031076A1

公开(公告)日：2008-02-07

申请号：US11872108

申请日：2007-10-15

Applicant: Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

Inventor： Gerald Bartley ,  Darryl Becker ,  Paul Dahlen ,  Philip Germann ,  Andrew Maki ,  Mark Maxson

IPC: G11C8/12

CPC classification number: G11C29/26 ,  G06F13/4243 ,  G11C5/04 ,  G11C8/12 ,  G11C29/32 ,  G11C2029/3202

Abstract: A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port. The memory chip is incorporated into a design structure that is embodied in a computer readable medium used for designing, manufacturing, or testing the memory chip.

Abstract translation: 适用于存储芯片的菊花链的存储芯片。 存储器芯片在第一输入端接收地址/命令字，确定地址命令字是否被引导到存储器芯片; 如果是这样，则存储器芯片访问存储器芯片上的阵列。 如果不是，则存储器芯片在第一输出上重新驱动地址/命令字。 作为地址/命令字的一部分或从第一数据总线端口接收写入数据。 接收总线时钟并用于接收和发送关于第一输入，第一输出，第一数据总线端口和第二数据总线端口的信息。 存储器芯片被并入设计结构中，其体现在用于设计，制造或测试存储器芯片的计算机可读介质中。