公开(公告)号：US20230351063A1

公开(公告)日：2023-11-02

申请号：US18333406

申请日：2023-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Kazuhiro Kurihara

IPC: G06F21/85 ,  G06F21/79 ,  G11C29/12 ,  G06F12/14 ,  G06F21/60

CPC classification number: G06F21/85 ,  G06F21/79 ,  G11C29/1201 ,  G06F12/1408 ,  G06F21/602

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

公开(公告)号：US20230351062A1

公开(公告)日：2023-11-02

申请号：US18218705

申请日：2023-07-06

Applicant: Pure Storage, Inc.

Inventor： S. Christopher Gladwin ,  Chuck Wilson Templeton ,  Jason K. Resch ,  Gary W. Grube

IPC: G06F21/85 ,  G06F21/72 ,  G06F21/80 ,  H04L9/32 ,  H04N21/222 ,  H04N21/2347 ,  H04N21/845 ,  H04L67/1097 ,  H04W12/033 ,  G06F3/06 ,  G06F11/10

CPC classification number: G06F21/85 ,  G06F21/72 ,  G06F21/80 ,  H04L9/3242 ,  H04N21/222 ,  H04N21/2347 ,  H04N21/8456 ,  H04L67/1097 ,  H04W12/033 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/067 ,  G06F11/1076 ,  G06F2211/1028 ,  H04L65/764

Abstract: A method includes obtaining input encoded data slices from memory of the storage network, where the input encoded data slices include a set of encoded data slices interspersed with a set of auxiliary data slices, where a data segment was error encoded into the set of encoded data slices, and where auxiliary data was error encoded into the set of auxiliary data slices. The method further includes obtaining de-selection information associated with the input encoded data slices and de-selecting the sequence of input encoded data slices based on the de-selection information to produce deselected encoded data slices. The method further includes error decoding at least a decode threshold number of encoded data slices of the deselected encoded data slices in accordance with error decoding parameters to reproduce the data segment. The method further includes outputting the data segment to a requesting computing device of the storage network.

公开(公告)号：US20230351028A1

公开(公告)日：2023-11-02

申请号：US17733562

申请日：2022-04-29

Applicant: Oracle International Corporation

Inventor： Nicholas Michel Raphaël Ponsini ,  Patrick Van Haver

IPC: G06F21/60 ,  G06F21/85 ,  H04L9/40

CPC classification number: G06F21/60 ,  G06F21/85 ,  H04L63/20

Abstract: Techniques for implementing and enforcing a security policy in a secure element are disclosed. The secure element enforces the security policy to grant and/or deny access, such as from an application processor, to configuration of the device peripheral components and access to data of the device peripheral components across one or more bus architectures, such as an I3C bus. Implementing an access control policy in a secure element allows execution of code within the isolated secure element hardware processor, preventing software attacks that may emanate from code running in the application processor. This design also benefits from hardware protections against physical attacks.

公开(公告)号：US11803666B2

公开(公告)日：2023-10-31

申请号：US17660080

申请日：2022-04-21

Applicant: CRYPTO4A TECHNOLOGIES INC.

Inventor： Bruno Couillard ,  Bradley Clare Ritchie ,  James Ross Goodman ,  Jean-Pierre Fiset

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/76 ,  G06F21/87 ,  G06F21/85 ,  G06F21/78

CPC classification number: G06F21/72 ,  G06F21/76 ,  G06F21/78 ,  G06F21/85 ,  G06F21/87 ,  H04L9/0897

Abstract: Described are various embodiments of a hardware security module, hardwired port interconnection matrix, and embedded communication channel resources operable on selected hardware port-specific data communicated via this matrix.

公开(公告)号：US20230334155A1

公开(公告)日：2023-10-19

申请号：US17850034

申请日：2022-06-27

Applicant: Shenzhen Fulian Fugui Precision Industry Co., Ltd.

Inventor： LIN ZHANG ,  WEN-XIAO LU ,  HUI-BO LIU ,  ZHI-YU DENG

IPC: G06F21/57 ,  G06F21/55 ,  G06F21/85 ,  G06F21/73 ,  G06F13/40

CPC classification number: G06F21/572 ,  G06F21/554 ,  G06F21/85 ,  G06F21/73 ,  G06F13/4027 ,  G06F13/4022

Abstract: A data center security control module able to connect with motherboards of different platforms such as Intel platform, AMD platform, and Ampere platform includes a baseboard management controller (BMC), a chip selection module, and a control module. The BMC outputs an alarm signal. The chip selection module includes N chip selection units, the chip selection unit outputting alarm signal to an external motherboard which is connected to the data center security control module. The control module obtains information as to motherboard type being Intel platform, or AMD platform, or Ampere platform and outputs a control signal to the chip selection module according to the motherboard type to start the chip selection unit associated with such motherboard type. The application also provides a data center security control module control method.

公开(公告)号：US11783097B2

公开(公告)日：2023-10-10

申请号：US17962627

申请日：2022-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Allen North ,  Per Torstein Roine ,  Eric Thierry Jean Peeters

IPC: G06F21/85 ,  G06F13/28 ,  G06F15/78

CPC classification number: G06F21/85 ,  G06F13/287 ,  G06F15/7807

Abstract: A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.

公开(公告)号：US11768964B2

公开(公告)日：2023-09-26

申请号：US17679009

申请日：2022-02-23

Applicant: Intel Corporation

Inventor： Manoj R. Sastry ,  Alpa Narendra Trivedi ,  Men Long

IPC: G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/06 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F21/85 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/0897 ,  G06F2207/7219 ,  G06F2211/008 ,  G06F2213/0038 ,  H04L2209/76

Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

公开(公告)号：US11763043B2

公开(公告)日：2023-09-19

申请号：US17129243

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Alpa Trivedi ,  Steffen Schulz ,  Patrick Koeberl

IPC: G06F15/177 ,  G06F9/00 ,  G06F21/85 ,  G06F30/398 ,  G06N3/04 ,  H04L9/08 ,  G06F9/30 ,  G06F9/50 ,  G06F15/78 ,  H04L9/40 ,  G06F11/07 ,  G06F30/331 ,  G06F9/38 ,  G06F11/30 ,  G06F119/12 ,  G06F21/76 ,  G06N3/08 ,  H04L9/00 ,  G06F111/04 ,  G06F30/31 ,  G06F21/30 ,  G06F21/53 ,  G06F21/57 ,  G06F21/73 ,  G06F21/74 ,  G06N20/00 ,  G06F21/71 ,  G06F21/44

CPC classification number: G06F21/85 ,  G06F9/30101 ,  G06F9/3877 ,  G06F9/505 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/0754 ,  G06F11/0793 ,  G06F11/3058 ,  G06F15/177 ,  G06F15/7825 ,  G06F15/7867 ,  G06F30/331 ,  G06F30/398 ,  G06N3/04 ,  H04L9/0877 ,  H04L63/0442 ,  H04L63/12 ,  H04L63/20 ,  G06F11/0772 ,  G06F11/3051 ,  G06F21/30 ,  G06F21/44 ,  G06F21/53 ,  G06F21/57 ,  G06F21/575 ,  G06F21/71 ,  G06F21/73 ,  G06F21/74 ,  G06F21/76 ,  G06F30/31 ,  G06F2111/04 ,  G06F2119/12 ,  G06F2221/034 ,  G06N3/08 ,  G06N20/00 ,  H04L9/008 ,  H04L9/0841

Abstract: An apparatus to facilitate enabling late-binding of security features via configuration security controller for accelerator devices is disclosed. The apparatus includes a security controller to initialize as part of a secure boot and attestation chain of trust; receive configuration data for portions of the security controller, the portions comprising components of the security controller capable of re-programming; verify and validate the configuration data to as originating from a secure and trusted source; and responsive to successful verification and validation of the configuration data, re-program the portions of the security controller based on the configuration data.

公开(公告)号：US11727156B2

公开(公告)日：2023-08-15

申请号：US17216568

申请日：2021-03-29

Applicant: Western Digital Technologies, Inc.

Inventor： Matthew Harris Klapman ,  Brian Edward Mastenbrook ,  Pongsanat Karmpeeraparpsontorn ,  Thantham Panyayodrat ,  Suksan Yaowaphak

IPC: G06F21/78 ,  G06F21/85 ,  G06F21/60 ,  G06F21/32

CPC classification number: G06F21/78 ,  G06F21/32 ,  G06F21/602 ,  G06F21/85 ,  G06F2221/0753

Abstract: An in-line security device to transfer cryptographic key material, the device comprising: a first connector configured to connect, via wire, with a host device; a second connector configured to connect, via wire, with a data storage device; a pass-through circuit between the first connector and the second connector to facilitate data communication between the host device and the data storage device; and a communication interface to send cryptographic key material to the data storage device via the second connector.

公开(公告)号：US11700174B2

公开(公告)日：2023-07-11

申请号：US16951198

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Nicolas Anquet ,  Loic Pallardy

IPC: H04L41/0803 ,  H04L41/0813 ,  H04L49/109 ,  G06F15/173 ,  G06F15/177 ,  G06F21/85

CPC classification number: H04L41/0813 ,  G06F15/177 ,  G06F15/17306 ,  H04L41/0803 ,  H04L49/109 ,  G06F21/85

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.