Amplifier bias control using tunneling current

    公开(公告)号:US11349446B2

    公开(公告)日:2022-05-31

    申请号:US17196914

    申请日:2021-03-09

    Abstract: An apparatus and method for using the known phenomena of quantum gate tunneling in semiconductor transistors to define the DC state of a charge-coupled amplifier is described. A first stage in which the tunneling current is bipolar (by pairing PMOS and NMOS transistors) in combination with a second stage with a controlled common mode voltage that can be used to control the first stage tunneling current, and thus the common mode voltage at the input. This can be done without the use of additional elements that may degrade performance or power consumption, since the input devices both process the input signal and maintain the DC operating point of the circuit. The approach may be advantageously used not only in charge-coupled amplifiers as described herein, but also in other capacitively coupled circuits such as charge balancing analog to digital converters (ADCs) and digital to analog converters (DACs).

    Method and Apparatus for Recovering Back-EMF Signal in a Switching Driver

    公开(公告)号:US20220014848A1

    公开(公告)日:2022-01-13

    申请号:US17372440

    申请日:2021-07-10

    Abstract: An apparatus and method for determining signals representative of events in the environment of a reactive transducer while being driven by a switching amplifier is disclosed. While the switching amplifier is in a zero voltage state, a signal capture circuit that is also in a zero voltage state is connected to the transducer for a relatively brief period of time during which a measurement is made of the residual current flow due to the inductance of the transducer. A prediction of the output signal is then subtracted from the signal measured across the transducer, reducing the overall range of the signal and increasing the relative size of the back-EMF signal compared to any remaining output signal. If desired, conventional echo cancellation can then be performed. The back-EMF signal can then be subjected to further processing by an analog-to-digital converter as known in the art.

    Programmable Impedance
    33.
    发明申请

    公开(公告)号:US20210133551A1

    公开(公告)日:2021-05-06

    申请号:US16806264

    申请日:2020-03-02

    Abstract: A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.

    Signal Processing Circuit Without Clock Mediation

    公开(公告)号:US20210036665A1

    公开(公告)日:2021-02-04

    申请号:US16940396

    申请日:2020-07-28

    Abstract: A signal processing circuit that achieves functionality similar to that of a switched capacitor circuit without the necessity a clock. The circuit compensates for finite open loop gain and for offset voltages in the components, allowing the circuit to “calculate” the result of a problem represented by the circuit essentially immediately upon the presentation of a new input or set of inputs. After the circuit is initialized to remove gain, an input is applied to the circuit, and propagates through the network and affects the state of amplifier outputs; the propagation from the input through capacitors to the ultimate output(s) of the circuit is the analog calculation taking place. The calculation is not mediated by a clock, but rather the calculation corresponds to the circuit's one-time response to the application of the inputs. Using these techniques complex signal processing circuits and even analog neural networks may be constructed.

    Use of differently delayed feedback to suppress metastability in noise shaping control loops

    公开(公告)号:US10784888B2

    公开(公告)日:2020-09-22

    申请号:US16454812

    申请日:2019-06-27

    Abstract: Described herein is a ΣΔ modulator with improved metastability in which the control loop remains stable. In one embodiment, the ΣΔ modulator utilizes differently delayed feedback to successive integrators of the control loop to suppress metastability errors without compromising the stability of the control loop. This is accomplished by including one or more quantizers in the control loop. This technique may be applied to control loops of at least second order, i.e., having two or more integrator stages, where at least one feedback term after the first is non-zero.

    Low power voice activity detector
    36.
    发明授权

    公开(公告)号:US12094488B2

    公开(公告)日:2024-09-17

    申请号:US17971626

    申请日:2022-10-23

    CPC classification number: G10L25/78

    Abstract: An apparatus and method for voice activity detection. A multiphase differential output rotating capacitive sampler achieves a frequency down conversion over as many specific frequency bands as are required for analysis. A chirp is created in the rotating sampler as the sum of arbitrary frequencies across the desired analysis band multiplied by a window function. The chirp is sampled at a rate of rotation synchronous with the last state of burst of the chirp, allowing a non-phase synchronous pattern in the coefficient values and allowing a high-Q and arbitrary decomposition of the signal. After the sample is taken, the next clock signal to the sampler is used to define the output voltage of the sampler by shorting the output, which is entirely capacitive, to ground. Processing occurs in the analog domain rather than digitally, avoiding the need for FFTs and allowing for greater speed and lower power consumption.

    Fast Fourier transform in analog domain

    公开(公告)号:US12063055B2

    公开(公告)日:2024-08-13

    申请号:US18077788

    申请日:2022-12-08

    CPC classification number: H04B1/04

    Abstract: An apparatus and method for performing a fast Fourier transform in the analog domain with passive components. A complex analog signal that is shift and scale invariant is derived from analog circuit properties. A butterfly circuit processes such signals using only passive components by mapping the Kirchhoff current and voltage laws into operations on the signals. A fast Fourier transform circuit of any desired width is constructed from such butterfly circuits. The passive networks require no power as the operations are on the presented signal; energy is taken from the source signal so no battery or power supply is needed. Thus, when the signal becomes quiescent, the power consumed is zero. Further there is no need of a clock or other timing device; rather, it is the operation of Kirchhoff laws in the network, which apply essentially upon arrival of the signal, that is made analogous to the desired operation.

    Programmable impedance
    38.
    发明授权

    公开(公告)号:US12050989B2

    公开(公告)日:2024-07-30

    申请号:US17818236

    申请日:2022-08-08

    CPC classification number: G06N3/065 G06F30/36 H03H17/0045

    Abstract: A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.

    Fast Fourier transforms with incomplete input data replacement

    公开(公告)号:US12038999B2

    公开(公告)日:2024-07-16

    申请号:US18080557

    申请日:2022-12-13

    CPC classification number: G06F17/142

    Abstract: A method for performing a fast Fourier transform. The bin spreading effect of conventional FFT methodology may be removed by a mathematical technique that relies on an incomplete replacement of the input data sequence. In the present approach this replacement is accomplished by a “round robin” method. In this approach no window function is required and the FFT calculation proceeds after each new sample is added round robin fashion to the input sequence. The resulting output bins from the FFT show the signal evolution with time, overlapping as in the known art but by a single sample. The output of a FFT so constructed is not time invariant, but rather there is a rotation present in each output bin when viewed as an analytical signal. This rotation is predictable and hence removeable, but is also exploitable as a means to remove the bin spill over.

    Combinatorial Logic Circuits With Feedback
    40.
    发明公开

    公开(公告)号:US20240220206A1

    公开(公告)日:2024-07-04

    申请号:US18602936

    申请日:2024-03-12

    CPC classification number: G06F7/5525 H03K19/20

    Abstract: Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.

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