公开(公告)号：US20230369428A1

公开(公告)日：2023-11-16

申请号：US17871403

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Sun ,  Wen-Kai Lin ,  Che-Hao Chang ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/66545

Abstract: Embodiments provide a two-tiered trench isolation structure under the epitaxial regions (e.g., epitaxial source/drain regions) of a nano-FET transistor device, and methods of forming the same. The first tier provides an isolation structure with a low k value. The second tier provides an isolation structure with a higher k value, with material greater density, and greater etch resistivity than the first tier isolation structure.

公开(公告)号：US20230261080A1

公开(公告)日：2023-08-17

申请号：US18297922

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Tzu-Chieh Su ,  Che-Hao Chang

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/66553

Abstract: A method includes forming a stack of layers comprising a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a first spacer layer extending into the lateral recesses, with the first spacer layer comprising a first dielectric material, depositing a second spacer layer on the first spacer layer, with the second spacer layer comprising a second dielectric material different from the first dielectric material, and trimming the first spacer layer and the second spacer layer to form inner spacers.

公开(公告)号：US20220376088A1

公开(公告)日：2022-11-24

申请号：US17815527

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

公开(公告)号：US11444177B2

公开(公告)日：2022-09-13

申请号：US16940226

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

公开(公告)号：US20210057546A1

公开(公告)日：2021-02-25

申请号：US17090121

申请日：2020-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US10833170B2

公开(公告)日：2020-11-10

申请号：US16592955

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.