公开(公告)号：US20200006145A1

公开(公告)日：2020-01-02

申请号：US16178819

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Chih-Hui Huang ,  Kuo-Ming Wu

IPC: H01L21/822 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

公开(公告)号：US20190067355A1

公开(公告)日：2019-02-28

申请号：US15688077

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Keng-Yu Chou ,  Yeur-Luen Tu

IPC: H01L27/146

Abstract: The present disclosure relates to an image sensor integrated chip having a deep trench isolation (DTI) structure having a reflective element. In some embodiments, the image sensor integrated chip includes an image sensing element arranged within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element and one or more absorption enhancement layers are arranged over and between the plurality of protrusions. A plurality of DTI structures are arranged within trenches disposed on opposing sides of the image sensing element and extend from the first side of the substrate to within the substrate. The plurality of DTI structures respectively include a reflective element having one or more reflective regions configured to reflect electromagnetic radiation. By reflecting electromagnetic radiation using the reflective elements, cross-talk between adjacent pixel regions is reduced, thereby improving performance of the image sensor integrated chip.

公开(公告)号：US10204822B2

公开(公告)日：2019-02-12

申请号：US15884304

申请日：2018-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hsien Chou ,  Hung-Ling Shih ,  Tsun-Kai Tsao ,  Ming-Huei Shen ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L21/02 ,  H01L21/762

Abstract: In a method for fabricating a semiconductor device, a trench is etched in a semiconductor substrate having a top surface, and a lining oxide layer is formed conformal to the trench. A negatively-charged liner covering the lining oxide layer and conformal to the trench is formed. The trench is partially filled with a flowable oxide to a level below the top surface of the semiconductor substrate, and the flowable oxide in the trench is cured. The negatively-charged liner above the cured flowable oxide is optionally removed. A silicon oxide is deposited in the remaining portion of the trench, and a planarization process is performed to remove excess portions of the silicon oxide over the top surface of the semiconductor substrate.

公开(公告)号：US20180061877A1

公开(公告)日：2018-03-01

申请号：US15803995

申请日：2017-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.

公开(公告)号：US09653507B2

公开(公告)日：2017-05-16

申请号：US14314193

申请日：2014-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L33/20

CPC classification number: H01L27/14685 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14687 ,  H01L33/20

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device.

公开(公告)号：US20240363671A1

公开(公告)日：2024-10-31

申请号：US18768642

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Chih-Yu Lai ,  Shih Pei Chou ,  Yen-Ting Chiang ,  Hsiao-Hui Tseng ,  Min-Ying Tsai

IPC: H01L27/146 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/14687 ,  H01L21/76229 ,  H01L27/1463 ,  H01L29/0653

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

公开(公告)号：US11610812B2

公开(公告)日：2023-03-21

申请号：US17038198

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hui Huang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Sheng-Chan Li

IPC: H01L21/00 ,  H01L21/768 ,  H01L25/00 ,  H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

公开(公告)号：US20210134663A1

公开(公告)日：2021-05-06

申请号：US17038198

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hui Huang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Sheng-Chan Li

IPC: H01L21/768 ,  H01L25/00 ,  H01L23/528 ,  H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

公开(公告)号：US10734285B2

公开(公告)日：2020-08-04

申请号：US16178819

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Chih-Hui Huang ,  Kuo-Ming Wu

IPC: H01L21/822 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

公开(公告)号：US20160020243A1

公开(公告)日：2016-01-21

申请号：US14867070

申请日：2015-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Wen-I Hsu ,  Tsun-Kai Tsao ,  Chih-Yu Lai ,  Jiech-Fun Lu ,  Yeur-Luen Tu

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/18

Abstract: The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.