公开(公告)号：US20230378067A1

公开(公告)日：2023-11-23

申请号：US18363515

申请日：2023-08-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsu-Chun KUO ,  Shin-Yi YANG ,  Yu-Chen CHAN ,  Shu-Wei LI ,  Meng-Pei LU ,  Ming-Han LEE

IPC: H01L23/532 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/53276 ,  H01L23/481 ,  H01L21/76879 ,  H01L21/7681

Abstract: A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.

公开(公告)号：US20230378030A1

公开(公告)日：2023-11-23

申请号：US18230284

申请日：2023-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/482 ,  H01L29/423 ,  H01L29/786 ,  H01L25/00 ,  H01L23/528 ,  H01L23/48 ,  H01L25/065 ,  H01L29/06

CPC classification number: H01L23/4822 ,  H01L29/42392 ,  H01L29/78696 ,  H01L25/50 ,  H01L23/5286 ,  H01L23/481 ,  H01L25/0652 ,  H01L29/0665

Abstract: Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.

公开(公告)号：US20230352409A1

公开(公告)日：2023-11-02

申请号：US17730453

申请日：2022-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Pei LU ,  Shin-Yi YANG ,  Ching-Fu YEH ,  Chin-Lung CHUNG ,  Cian-Yu CHEN ,  Yun-Chi CHIANG ,  Tsu-Chun KUO ,  Ming-Han LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L23/53266 ,  H01L23/53252 ,  H01L23/53223 ,  H01L21/76877 ,  H01L23/5226 ,  H01L21/76831 ,  H01L21/76846

Abstract: A semiconductor device includes a substrate and an interconnect layer disposed on the substrate. The interconnect layer includes a dielectric layer and an interconnect extending through the dielectric layer. The interconnect includes a bulk metal region and a single barrier/liner layer, which serves as both a barrier layer and a liner layer and which is disposed to separate the bulk metal region from the dielectric layer.

公开(公告)号：US20230066891A1

公开(公告)日：2023-03-02

申请号：US17460909

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsu-Chun KUO ,  Shin-Yi YANG ,  Yu-Chen CHAN ,  Shu-Wei LI ,  Meng-Pei LU ,  Ming-Han LEE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/48

Abstract: A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.

公开(公告)号：US20230062416A1

公开(公告)日：2023-03-02

申请号：US17460812

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chieh-Han WU ,  Hwei-Jay CHU ,  An-Dih YU ,  Tzu-Hui WEI ,  Cheng-Hsiung TSAI ,  Chung-Ju LEE ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L29/06 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.

公开(公告)号：US20220319989A1

公开(公告)日：2022-10-06

申请号：US17217016

申请日：2021-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shu-Wei LI ,  Guanyu LUO ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric material and a conductive feature extending through the dielectric material. The conductive feature includes a conductive material and has a first top surface. The structure further includes a dummy conductive feature disposed adjacent the conductive feature in the dielectric material, and the dummy conductive feature has a second top surface substantially co-planar with the first top surface. An air gap is formed in the dummy conductive feature.

公开(公告)号：US20220293546A1

公开(公告)日：2022-09-15

申请号：US17383355

申请日：2021-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through a RDL structure formed between the two or more integrated circuit dies.

公开(公告)号：US20220285292A1

公开(公告)日：2022-09-08

申请号：US17381561

申请日：2021-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shau-Lin SHUE ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L23/58 ,  H01L23/522 ,  H01L23/00 ,  H01L21/66

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.