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    Fast signal conductor networks for programmable logic devices
    33.
    发明授权
    Fast signal conductor networks for programmable logic devices 有权
    用于可编程逻辑器件的快速信号导线网络

    公开(公告)号：US06373280B1

    公开(公告)日：2002-04-16

    申请号：US09795796

    申请日：2001-02-28

    Applicant: Christopher F. Lane ,  Srinivas T. Reddy

    Inventor： Christopher F. Lane ,  Srinivas T. Reddy

    IPC: A03K19177

    CPC classification number: H03K19/17736 ,  H03K19/17792

    Abstract: A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.

    Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该可编程逻辑区域以这种区域的交叉行和列的二维阵列布置在器件上。 在设备上提供了所谓的“快速导体”网络，用于将相对较少数量的信号快速有效地分配到设备上的基本上任何逻辑区域。 快速导体网络具有几个主导体，其在一个方向上基本上平分阵列（例如，通过平行于列轴线延伸）。 一些主导体可以携带离开设备的信号。 其他主导体可以携带在设备上产生的信号。 网络还包括横向于主导体（例如，沿着每一排逻辑区域）延伸的次级导体。 提供可编程逻辑连接器，用于选择性地将信号从主导体施加到次级导体，并从次导体到逻辑区域。

    Programmable logic device memory array circuit having combinable single-port memory arrays
    34.
    发明授权
    Programmable logic device memory array circuit having combinable single-port memory arrays 失效
    具有可组合单端口存储器阵列的可编程逻辑器件存储器阵列电路

    公开(公告)号：US06288970B1

    公开(公告)日：2001-09-11

    申请号：US09107926

    申请日：1998-06-30

    Applicant: Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    Inventor： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    IPC: G11C800

    CPC classification number: G11C7/1075 ,  G11C7/10 ,  G11C8/16 ,  G11C11/005

    Abstract: A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable singleport memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.

    Abstract translation: 提供了一种可编程逻辑器件存储器阵列电路，其包含一对相关联的可组合单端口存储器阵列。 存储器阵列电路可以具有可变的深度和宽度。 如果需要，可组合的单端口存储器阵列可以独立地操作。 或者，一对可组合单端口存储器阵列可以组合以形成双端口存储器阵列。 当单端口存储器阵列组合以形成双端口存储器阵列时，来自第一可组合单端口存储器阵列的电路用于执行写入操作，并且来自第二可组合单端口存储器阵列的电路被用于 执行阅读操作。 双端口存储器阵列功能的可用性允许用户实现诸如先入先出缓冲器和需要执行并发读写操作的其他电路的电路。 当不需要这样的双端口功能时，两个单端口存储器阵列可用于实现期望的逻辑设计。

    Redundancy circuitry for programmable logic devices with interleaved input circuits
    37.
    发明授权
    Redundancy circuitry for programmable logic devices with interleaved input circuits 失效

    公开(公告)号：US6107820A

    公开(公告)日：2000-08-22

    申请号：US82081

    申请日：1998-05-20

    Applicant: David E. Jefferson ,  Srinivas T. Reddy

    Inventor： David E. Jefferson ,  Srinivas T. Reddy

    IPC: H03K19/173 ,  G06F11/20 ,  G06F7/38

    CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

    Abstract: Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.

    Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
    38.
    发明授权
    Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices 失效
    减少可编程逻辑器件中硅处理缺陷影响的手段和装置

    公开(公告)号：US5592102A

    公开(公告)日：1997-01-07

    申请号：US545437

    申请日：1995-10-19

    Applicant: Christopher F. Lane ,  Srinivas T. Reddy ,  Bonnie I. Wang

    Inventor： Christopher F. Lane ,  Srinivas T. Reddy ,  Bonnie I. Wang

    IPC: G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  H01L25/00

    CPC classification number: H03K19/1776 ,  G06F15/7867 ,  H03K19/17736 ,  H03K19/17764

    Abstract: A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.

    Abstract translation: 可编程逻辑阵列集成电路具有几个可编程逻辑电路的常规列和备用列，该备用列包括包含在常规列中的可编程逻辑电路的子集。 在备用列中复制的常规列中的电路中存在缺陷的情况下，由此复制的常规列逻辑功能从列移动到列，使得备用列电路被使用，并且缺陷规则 不使用列电路。 在备用列中未重复的常规列函数不会移动。 用于编程列的数据有选择地路由到具有或不具有列移位的列，这取决于该数据是用于在备用列中是否被复制的功能。

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