Invention Grant
- Patent Title: Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
- Patent Title (中): 减少可编程逻辑器件中硅处理缺陷影响的手段和装置
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Application No.: US545437Application Date: 1995-10-19
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Publication No.: US5592102APublication Date: 1997-01-07
- Inventor: Christopher F. Lane , Srinivas T. Reddy , Bonnie I. Wang
- Applicant: Christopher F. Lane , Srinivas T. Reddy , Bonnie I. Wang
- Applicant Address: CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: CA San Jose
- Main IPC: G06F11/20
- IPC: G06F11/20 ; G06F15/78 ; H03K19/177 ; H01L25/00
Abstract:
A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
Public/Granted literature
- US4002317A Casting mold assembly Public/Granted day:1977-01-11
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