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    Programmable logic device memory array circuit having combinable single-port memory arrays
    31.
    发明授权
    Programmable logic device memory array circuit having combinable single-port memory arrays 失效
    具有可组合单端口存储器阵列的可编程逻辑器件存储器阵列电路

    公开(公告)号：US06288970B1

    公开(公告)日：2001-09-11

    申请号：US09107926

    申请日：1998-06-30

    Applicant: Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    Inventor： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    IPC: G11C800

    CPC classification number: G11C7/1075 ,  G11C7/10 ,  G11C8/16 ,  G11C11/005

    Abstract: A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable singleport memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.

    Abstract translation: 提供了一种可编程逻辑器件存储器阵列电路，其包含一对相关联的可组合单端口存储器阵列。 存储器阵列电路可以具有可变的深度和宽度。 如果需要，可组合的单端口存储器阵列可以独立地操作。 或者，一对可组合单端口存储器阵列可以组合以形成双端口存储器阵列。 当单端口存储器阵列组合以形成双端口存储器阵列时，来自第一可组合单端口存储器阵列的电路用于执行写入操作，并且来自第二可组合单端口存储器阵列的电路被用于 执行阅读操作。 双端口存储器阵列功能的可用性允许用户实现诸如先入先出缓冲器和需要执行并发读写操作的其他电路的电路。 当不需要这样的双端口功能时，两个单端口存储器阵列可用于实现期望的逻辑设计。

    Redundancy circuitry for programmable logic devices with interleaved input circuits
    34.
    发明授权
    Redundancy circuitry for programmable logic devices with interleaved input circuits 失效

    公开(公告)号：US6107820A

    公开(公告)日：2000-08-22

    申请号：US82081

    申请日：1998-05-20

    Applicant: David E. Jefferson ,  Srinivas T. Reddy

    Inventor： David E. Jefferson ,  Srinivas T. Reddy

    IPC: H03K19/173 ,  G06F11/20 ,  G06F7/38

    CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

    Abstract: Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.

    Look-up table using multi-level decode
    35.
    发明授权
    Look-up table using multi-level decode 失效

    公开(公告)号：US6037829A

    公开(公告)日：2000-03-14

    申请号：US591121

    申请日：1996-01-25

    Applicant: Srinivas T. Reddy ,  Anil Gupta

    Inventor： Srinivas T. Reddy ,  Anil Gupta

    IPC: H03K17/00 ,  H03K17/693 ,  H03K17/62 ,  G11C8/00

    CPC classification number: H03K17/693 ,  H03K17/005

    Abstract: A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

    Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
    36.
    发明授权
    Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices 失效
    减少可编程逻辑器件中硅处理缺陷影响的手段和装置

    公开(公告)号：US5592102A

    公开(公告)日：1997-01-07

    申请号：US545437

    申请日：1995-10-19

    Applicant: Christopher F. Lane ,  Srinivas T. Reddy ,  Bonnie I. Wang

    Inventor： Christopher F. Lane ,  Srinivas T. Reddy ,  Bonnie I. Wang

    IPC: G06F11/20 ,  G06F15/78 ,  H03K19/177 ,  H01L25/00

    CPC classification number: H03K19/1776 ,  G06F15/7867 ,  H03K19/17736 ,  H03K19/17764

    Abstract: A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.

    Abstract translation: 可编程逻辑阵列集成电路具有几个可编程逻辑电路的常规列和备用列，该备用列包括包含在常规列中的可编程逻辑电路的子集。 在备用列中复制的常规列中的电路中存在缺陷的情况下，由此复制的常规列逻辑功能从列移动到列，使得备用列电路被使用，并且缺陷规则 不使用列电路。 在备用列中未重复的常规列函数不会移动。 用于编程列的数据有选择地路由到具有或不具有列移位的列，这取决于该数据是用于在备用列中是否被复制的功能。

    System and method for optimizing routing lines in a programmable logic device
    39.
    发明授权
    System and method for optimizing routing lines in a programmable logic device 有权
    用于优化可编程逻辑器件中路由线路的系统和方法

    公开(公告)号：US06895570B2

    公开(公告)日：2005-05-17

    申请号：US10057232

    申请日：2002-01-25

    Applicant: David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

    Inventor： David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

    IPC: G06F17/50 ,  H01L21/82 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  G06F17/5054 ,  G06F17/5077

    Abstract: An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.A routing architecture is an array that includes rows and columns of function blocks. The columns of the array are connected with horizontal lines (“H-line”) and the rows of the array are connected with vertical lines (“V-line). The types of H-lines include a H4 line that spans four function blocks, a H8 line that spans eight function blocks, and a H24 line that spans twenty-four function blocks. The types of V-lines include a V4 line that spans four function blocks, a V8 line that spans eight function blocks, and a V16 line that spans sixteen function blocks.

    Abstract translation: 本发明的实施例涉及将可编程逻辑器件（“PLD”）内的多个功能块互连的导线。 确定电线最佳物理长度。 具有最佳物理长度的导线尽可能快地将信号沿导线传送。 在PLD中使用的一些电线具有与电最佳物理长度基本相同的物理长度或电学最佳物理长度的调整以考虑非电学考虑。 如本文所使用的物理长度是测量的线的长度。 如本文所使用的，线的逻辑长度是导线跨越的功能块的数量。 假设功能块具有不同的高度和宽度，则线的逻辑长度根据线的方向而变化。 路由架构是包括功能块的行和列的数组。 数组的列与水平线（“H-line”）连接，阵列与垂直线（“V线”）连接，H线的类型包括四条功能块的H4线 ，一个跨越八个功能块的H8线，以及跨越二十四个功能块的H24线，V线的类型包括跨越四个功能块的V4线，跨越八个功能块的V8线，以及V16线 线跨越十六个功能块。

    Routing architecture for a programmable logic device
    40.
    发明授权
    Routing architecture for a programmable logic device 有权

    公开(公告)号：US06630842B1

    公开(公告)日：2003-10-07

    申请号：US10140287

    申请日：2002-05-06

    Applicant: David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    Inventor： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    IPC: H03K19177

    CPC classification number: H03K19/17736

    Abstract: An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides. In this configuration, the width of one of the first channel, the second channel, or the third channel differs from the width of another one of those channels. Input multiplexers route signals from the wires of the channels to the inputs of the function block. Output multiplexers and drivers drive the outputs of the function block through the wires of the channels. By placing the input multiplexers and the output multiplexers in certain relative arrangements, the logical distance that an output signal from the function block can travel on a wire is increased and that signal can be looped back to itself. In addition, each of the inputs and the outputs of the function block can be connected to both horizontal and vertical channels, and an output of the function block can be directly connected to an input of an adjacent function block.

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