公开(公告)号：US10699160B2

公开(公告)日：2020-06-30

申请号：US16110664

申请日：2018-08-23

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Sehwan Lee ,  Leesup Kim ,  Hyeonuk Kim ,  Jaehyeong Sim ,  Yeongjae Choi

IPC: G06K9/62 ,  G06N3/04 ,  G06N3/063

Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.

公开(公告)号：US20200026979A1

公开(公告)日：2020-01-23

申请号：US16552850

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/08

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US12056595B2

公开(公告)日：2024-08-06

申请号：US16158660

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan Lee ,  Namjoon Kim ,  Joonho Song ,  Junwoo Jang

IPC: G06N3/063 ,  G06F17/15 ,  G06N3/04 ,  G06N3/045 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F17/15 ,  G06N3/04 ,  G06N3/045 ,  G06T1/20

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network, the method includes determining operands from input feature maps and kernels, on which a convolution operation is to be performed, dispatching operand pairs combined from the determined operands to multipliers in a convolution operator, generating outputs by performing addition and accumulation operations with respect to results of multiplication operations, and obtaining pixel values of output feature maps corresponding to a result of the convolution operation based on the generated outputs.

公开(公告)号：US12056591B2

公开(公告)日：2024-08-06

申请号：US18453615

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan Lee

IPC: G06N3/04 ,  G06F17/15 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06F17/15 ,  G06N3/045

Abstract: Provided are a method of performing a convolution operation between a kernel and an input feature map based on reuse of the input feature map, and a neural network apparatus using the method. The neural network apparatus generates output values of an operation between each of weights of a kernel and an input feature map, and generates an output feature map by accumulating the output values at positions in the output feature map that are set based on positions of the weights in the kernel.

公开(公告)号：US20240256828A1

公开(公告)日：2024-08-01

申请号：US18601739

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US12039430B2

公开(公告)日：2024-07-16

申请号：US17098589

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Arnab Roy ,  Saptarsi Das ,  Ankur Deshwal ,  Kiran Kolar Chandrasek Haran ,  Sehwan Lee

IPC: G06N3/04 ,  G06F7/544 ,  G06N3/045

CPC classification number: G06N3/045 ,  G06F7/5443

Abstract: A method for computing an inner product on a binary data, a ternary data, a non-binary data, and a non-ternary data using an electronic device. The method includes calculating the inner product on a ternary data, designing a fused bitwise data path to support the inner product calculation on the binary data and the ternary data, designing a FPL data path to calculate an inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data, and distributing the inner product calculation for the binary data and the ternary data and the inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data in the fused bitwise data path and the FPL data path.

公开(公告)号：US12014505B2

公开(公告)日：2024-06-18

申请号：US16564215

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan Lee

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06T1/20 ,  G06T7/33

CPC classification number: G06T7/33 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T1/20 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2210/52

Abstract: A neural network apparatus is disclosed, where the neural network apparatus includes one or more processors comprising a controller and one or more processing units. The controller is configured to determine a shared operand to be shared in parallelized operations as being either one of a pixel value among pixel values of an input feature map and a weight value among weight values of a kernel, based on either one or both of a feature of the input feature map and a feature of the kernel. The one or more processing units are configured to perform the parallelized operations based on the determined shared operand.

公开(公告)号：US11960999B2

公开(公告)日：2024-04-16

申请号：US18304574

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho Song ,  Sehwan Lee ,  Junwoo Jang

IPC: G06N3/08 ,  G06F17/15 ,  G06N3/04 ,  G06N3/045

CPC classification number: G06N3/08 ,  G06F17/153 ,  G06N3/04 ,  G06N3/045

Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.

公开(公告)号：US11954574B2

公开(公告)日：2024-04-09

申请号：US16446610

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/15 ,  G06F17/16 ,  G06N3/08 ,  G06T9/00

CPC classification number: G06N3/04 ,  G06F17/153 ,  G06F17/16 ,  G06N3/08 ,  G06T9/002 ,  G06F9/3001

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.

公开(公告)号：US11769037B2

公开(公告)日：2023-09-26

申请号：US16558493

申请日：2019-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan Lee

IPC: G06N3/04 ,  G06F17/15 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06F17/15 ,  G06N3/045

Abstract: Provided are a method of performing a convolution operation between a kernel and an input feature map based on reuse of the input feature map, and a neural network apparatus using the method. The neural network apparatus generates output values of an operation between each of weights of a kernel and an input feature map, and generates an output feature map by accumulating the output values at positions in the output feature map that are set based on positions of the weights in the kernel.