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    Method and apparatus with neural network performing deconvolution
    1.
    发明授权
    Method and apparatus with neural network performing deconvolution 有权

    公开(公告)号：US10885433B2

    公开(公告)日：2021-01-05

    申请号：US16107717

    申请日：2018-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joonho Song ,  Sehwan Lee ,  Junwoo Jang

    IPC: G06N3/08 ,  G06N3/04

    Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.

    Method and apparatus for allocating memory space for driving neural network
    2.
    发明授权
    Method and apparatus for allocating memory space for driving neural network 有权

    公开(公告)号：US11675507B2

    公开(公告)日：2023-06-13

    申请号：US17394447

    申请日：2021-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonho Song

    IPC: G06F3/06 ,  G06N3/04

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06N3/04

    Abstract: A method of allocating a memory for driving a neural network including obtaining first capacity information of a space to store an input feature map of a first layer from among the layers of the neural network, and second capacity information of a space to store an output feature map of the first layer, and allocating a first storage space to store the input feature map in the memory based on an initial address value of the memory and the first capacity information and a second storage space to store the output feature map in the memory based on a last address value of the memory and the second capacity information.

    Arithmetic apparatus, operating method thereof, and neural network processor
    7.
    发明授权
    Arithmetic apparatus, operating method thereof, and neural network processor 有权

    公开(公告)号：US12175208B2

    公开(公告)日：2024-12-24

    申请号：US16989391

    申请日：2020-08-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinook Song ,  Daekyeung Kim ,  Junseok Park ,  Joonho Song ,  Sehwan Lee ,  Junwoo Jang ,  Yunkyo Cho

    IPC: G06F7/544 ,  G06N3/063

    Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

    Method and apparatus with neural network convolution operations
    8.
    发明授权
    Method and apparatus with neural network convolution operations 有权

    公开(公告)号：US11853888B2

    公开(公告)日：2023-12-26

    申请号：US18089696

    申请日：2022-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joonho Song ,  Namjoon Kim ,  Sehwan Lee ,  Deokjin Joo

    IPC: G06N3/08 ,  G06F7/74 ,  G06N20/00

    CPC classification number: G06N3/08 ,  G06F7/74 ,  G06N20/00

    Abstract: A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.

    Method and apparatus with neural network convolution operations
    9.
    发明授权
    Method and apparatus with neural network convolution operations 有权

    公开(公告)号：US11568243B2

    公开(公告)日：2023-01-31

    申请号：US16704290

    申请日：2019-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Joonho Song ,  Namjoon Kim ,  Sehwan Lee ,  Deokjin Joo

    IPC: G06N3/08 ,  G06F7/74 ,  G06N20/00

    Abstract: A processor-implemented method of performing convolution operations in a neural network includes generating a plurality of first sub-bit groups and a plurality of second sub-bit groups, respectively from at least one pixel value of an input feature map and at least one predetermined weight, performing a convolution operation on a first pair that includes a first sub-bit group including a most significant bit (MSB) of the at least one pixel value and a second sub-bit group including an MSB of the at least one predetermined weight, based on the plurality of second sub-bit groups, obtaining a maximum value of a sum of results for convolution operations of remaining pairs excepting the first pair, and based on a result of the convolution operation on the first pair and the maximum value, determining whether to perform the convolution operations of the remaining pairs.

    Three-dimensional stacked memory device and method
    10.
    发明授权
    Three-dimensional stacked memory device and method 有权

    公开(公告)号：US11386975B2

    公开(公告)日：2022-07-12

    申请号：US16456094

    申请日：2019-06-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Shinhaeng Kang ,  Joonho Song ,  Seungwon Lee

    IPC: G06F11/20 ,  G06F12/0815 ,  G11C29/38 ,  H01L25/065 ,  H01L25/18 ,  G11C29/00 ,  G01R31/3193

    Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

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