公开(公告)号：US10671464B2

公开(公告)日：2020-06-02

申请号：US15850604

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonhee Oh ,  Je Min Ryu ,  Reum Oh ,  Jaeyoun Youn

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/0802 ,  G11C16/10 ,  G06F11/10 ,  G11C29/48 ,  G11C29/04

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.

公开(公告)号：US10262699B2

公开(公告)日：2019-04-16

申请号：US16106492

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Reum Oh ,  Je-Min Ryu ,  Pavan Kumar Kasibhatla

IPC: G11C5/02 ,  G11C29/48 ,  G11C29/12 ,  G11C7/10 ,  G06F12/0893 ,  G06F12/084 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

公开(公告)号：US20180189127A1

公开(公告)日：2018-07-05

申请号：US15850604

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonhee Oh ,  Je Min Ryu ,  Reum Oh ,  Jaeyoun Youn

IPC: G06F11/07 ,  G11C16/10 ,  G11C29/48 ,  G06F12/0802

CPC classification number: G06F11/0721 ,  G06F11/0736 ,  G06F11/1048 ,  G06F12/0802 ,  G11C16/10 ,  G11C29/48 ,  G11C2029/0409

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.