公开(公告)号：US20210126079A1

公开(公告)日：2021-04-29

申请号：US16988984

申请日：2020-08-10

Applicant: Samsung Display Co., LTD.

Inventor： Kang Moon JO ,  Chong Chul CHAI ,  Jun Hyun PARK ,  An Su LEE

IPC: H01L27/32

Abstract: An organic light emitting diode display includes a substrate, a semiconductor pattern disposed on the substrate, a first conductive layer disposed on the semiconductor pattern and including a first gate electrode having an island-shaped structure, a second gate electrode having an island-shaped structure, and a third gate electrode having an island-shaped structure, and a second conductive layer disposed on the first conductive layer and including a first initialization voltage line overlapping the first gate electrode, a scan line overlapping the second gate electrode, and a control signal line overlapping the third gate electrode, where the control signal line is electrically connected to the third gate electrode, the scan line is electrically connected to the second gate electrode, and the first initialization voltage line, the scan line, and the control signal line extend in a first direction.

公开(公告)号：US20210125560A1

公开(公告)日：2021-04-29

申请号：US17062971

申请日：2020-10-05

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun PARK ,  Chong Chul CHAI ,  Young Wan SEO ,  An Su LEE ,  Bo Yong CHUNG ,  Kang Moon JO

IPC: G09G3/3258

Abstract: A pixel circuit includes a first switching element including a control electrode connected to a first node, an input electrode which receives a first power voltage and an output electrode connected to a third node, a second switching element including a control electrode which receives a compensation gate signal, an input electrode connected to a second node and an output electrode connected to the third node, a third switching element including a control electrode which receives a write gate signal, an input electrode connected to the first node and an output electrode connected to the second node, a storage capacitor including a first electrode which receives an initialization voltage and a second electrode connected to the first node, a program capacitor which receives a data voltage and connected to the second node, and an organic light emitting element connected to the third node and which receives a second power voltage.

公开(公告)号：US20210020725A1

公开(公告)日：2021-01-21

申请号：US16886075

申请日：2020-05-28

Applicant: Samsung Display Co., LTD.

Inventor： Jun Hyun PARK ,  Dong Woo KIM ,  Kang Moon JO ,  Sung Jae MOON

IPC: H01L27/32

Abstract: A display device including a substrate including a display area and an opening area therein, a data conductive layer on the substrate and including a source electrode and a voltage wiring in the opening area, a protective layer on the data conductive layer and covering the source electrode and the voltage wiring, a pixel electrode layer including a pixel electrode connected to the source electrode through a first contact hole, and an electrode pattern connected to the voltage wiring through a second contact hole, a pixel defining layer including an opening exposing the pixel electrode and a hole exposing the electrode pattern, a light emitting layer on the pixel defining layer and a common electrode on the light emitting layer, wherein the hole does not overlap the first and second contact holes.

公开(公告)号：US20200333391A1

公开(公告)日：2020-10-22

申请号：US16851590

申请日：2020-04-17

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun PARK ,  Dong Woo KIM ,  An Su LEE ,  Kang Moon JO

IPC: G01R31/28 ,  G01R31/56

Abstract: A display panel includes: a pixel region comprising a plurality of pixels; an open/short test region comprising a plurality of open/short test pads; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal, wherein the plurality of stages is spaced apart by a first distance from the pixel region, and the dummy stage is spaced apart by a second distance greater than the first distance from the open/short test region.

公开(公告)号：US20200327854A1

公开(公告)日：2020-10-15

申请号：US16697022

申请日：2019-11-26

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun PARK ,  Dong Woo KIM ,  An Su LEE ,  Kang Moon JO

IPC: G09G3/3266

Abstract: There are provided a gate driver and a display device including the same. The gate driver includes: a first scan driver; a first sensing driver; a first scan clock line; and a first sensing clock line. The first scan clock line includes a first scan clock main line extending in one direction, and a first scan clock connection line connected to the first scan clock main line and the first scan driver. The first sensing clock line includes a first sensing clock main line extending in one direction, and a first sensing clock connection line connected to the first sensing clock main line and the first sensing driver. The first scan clock main line is closer to each of the first scan driver and the first sensing driver than the first sensing clock main line.

公开(公告)号：US20200321427A1

公开(公告)日：2020-10-08

申请号：US16834460

申请日：2020-03-30

Applicant: Samsung Display Co., LTD.

Inventor： Jun Hyun PARK ,  Dong Woo KIM ,  Sung Jae MOON ,  Kang Moon JO

IPC: H01L27/32

Abstract: A display device includes a substrate, a metal layer disposed on the substrate, a first conductive layer including a lower pattern disposed on the metal layer, an active layer disposed on the first conductive layer, a second conductive layer disposed on the active layer and including a first gate electrode, a pixel electrode disposed on the second conductive layer, and an emission layer and a common electrode disposed on the pixel electrode.

公开(公告)号：US20200279900A1

公开(公告)日：2020-09-03

申请号：US16800634

申请日：2020-02-25

Applicant: Samsung Display Co., LTD.

Inventor： Jun Hyun PARK ,  Dong Woo KIM ,  Sung Jae MOON ,  Kang Moon JO

IPC: H01L27/32 ,  H01L49/02 ,  H01L27/15

Abstract: A display device includes a substrate, a first transistor disposed on the substrate and including a first active pattern having a first channel region, a first source region, a first drain region, and a first gate electrode, a first insulating layer disposed on the first transistor, a first electrode disposed on the first insulating layer and electrically connected to the first drain region, a second insulating layer having a first opening disposed on the first electrode, a first contact member disposed on the second insulating layer and electrically connected to the first electrode through the first opening, a third insulating layer having a second opening disposed on the first contact member, and a pixel electrode disposed on the third insulating layer and electrically connected to the first contact member through the second opening, and an emission layer disposed on the pixel electrode.

公开(公告)号：US20200219453A1

公开(公告)日：2020-07-09

申请号：US16736993

申请日：2020-01-08

Applicant: SAMSUNG DISPLAY CO LTD.

Inventor： JUN HYUN PARK ,  An Su LEE ,  Dong Woo KIM ,  Sung Jae MOON ,  Kang Moon JO

IPC: G09G3/3291 ,  H01L27/32

Abstract: An organic light emitting diode display including: a data wiring that includes a main data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wiring that includes a main driving voltage line disposed in the display area and a first driving voltage line that is connected with the main driving voltage line and disposed in the peripheral area while extending in a first direction; and a driving low-voltage wiring that includes a cathode extending to the peripheral area while overlapping the display area, and a plurality of first driving low-voltage connection portions that are connected with the cathode and disposed in the peripheral area, wherein each of the plurality of first driving low-voltage connection portions comprises a wiring portion extended in the first direction and a pad portion electrically connected with the wiring portion.

公开(公告)号：US20160218116A1

公开(公告)日：2016-07-28

申请号：US14958011

申请日：2015-12-03

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Moon JO ,  Kyung-Hoon Kim ,  Dong Woo Kim ,  Il Gon Kim ,  Se Hyoung Cho

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L23/31 ,  H01L21/768 ,  H01L21/441 ,  H01L23/29 ,  H01L29/786 ,  H01L21/56

CPC classification number: H01L27/124 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3171 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display device includes: a gate electrode, a gate line, and data lines on a substrate, the data lines in a same layer as the gate line; a gate insulating layer on the gate line; a semiconductor member on the gate insulating layer; an etch stopper layer on the semiconductor member and the gate insulating layer; a first passivation layer on the etch stopper layer; a source electrode on the first passivation layer and the etch stopper layer and connected to the data lines; a drain electrode on the etch stopper layer; a common electrode on the first passivation layer and separated from the source electrode and the drain electrode; a second passivation layer on the source electrode, the drain electrode and the common electrode; and a pixel electrode on the second passivation layer and connected to the drain electrode.

Abstract translation: 显示装置包括：栅电极，栅极线和衬底上的数据线，数据线与栅极线在同一层中; 栅极线上的栅极绝缘层; 栅极绝缘层上的半导体部件; 半导体部件上的蚀刻停止层和栅极绝缘层; 蚀刻停止层上的第一钝化层; 在第一钝化层上的源电极和蚀刻停止层并连接到数据线; 蚀刻停止层上的漏电极; 在第一钝化层上的公共电极并与源电极和漏电极分离; 源电极，漏电极和公共电极上的第二钝化层; 以及在所述第二钝化层上并连接到所述漏电极的像素电极。

公开(公告)号：US20150187813A1

公开(公告)日：2015-07-02

申请号：US14659120

申请日：2015-03-16

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho JUNG ,  Young Joo CHOI ,  Joon Geol KIM ,  Kang Moon JO ,  Sho Yeon KIM ,  Byung Hwan CHU ,  Woo Geun LEE ,  Woo-Seok JEON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。