METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS
    31.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS 有权
    使用TRENCH隔离区域制造半导体器件以维持通道应力的方法

    公开(公告)号:US20150099335A1

    公开(公告)日:2015-04-09

    申请号:US14048282

    申请日:2013-10-08

    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.

    Abstract translation: 用于形成互补金属氧化物半导体(CMOS)半导体器件的方法包括在绝缘体上硅(SOI)晶片的半导体层中形成横向相邻的第一和第二有源区。 应力诱导层形成在第一有源区上方以赋予应力。 沟槽隔离区形成为包围应力诱导层的第一有源区和相邻部分。 去除应力诱导层,离开沟槽隔离区域以保持赋予第一有源区域的应力。

    METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT
    32.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT 有权
    使用间隔器进行源/漏限制的半导体器件的制造方法

    公开(公告)号:US20140357040A1

    公开(公告)日:2014-12-04

    申请号:US13905586

    申请日:2013-05-30

    Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

    Abstract translation: 制造半导体器件的方法包括在第一半导体材料层上形成用于至少一个栅极叠层的第一间隔物,以及与邻近所述至少一个栅极的每个源区和漏区形成相应的第二间隔物。 每个第二间隔件具有一对相对的侧壁和与其连接的端壁。 该方法包括用第二半导体材料填充源区和漏区,而第一和第二间隔件提供约束。

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