公开(公告)号：US08453043B2

公开(公告)日：2013-05-28

申请号：US12880960

申请日：2010-09-13

Applicant: Jinn-Yeh Chien ,  Chih-Hsien Chang

Inventor： Jinn-Yeh Chien ,  Chih-Hsien Chang

IPC: G06F7/02 ,  G06F11/00 ,  H03M13/00

CPC classification number: G11C29/12 ,  G11C29/36 ,  G11C29/38

Abstract: System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification.

Abstract translation: 公开了通过使用内置抖动调制电路来测试抖动容限的系统和方法。 一个实施例包括抖动调制电路，发射机，接收机和数据比较单元。 抖动调制电路包括多个数据锁存器，相位选择块和多相时钟发生器。 多相时钟发生器能够产生具有不同相移的多个信号，其中具有来自系统时钟信号的相移的一个信号由相位选择块选择。 所选择的信号通过在多个数据锁存器中注入抖动来改变数据。 抖动污染的数据通过发射机和接收机传输到数据比较单元。 片上测试电路将抖动污染数据与原始数据进行比较，并计算误码率，以确定该半导体器件的抖动容限是否满足规范。

公开(公告)号：US20120262209A1

公开(公告)日：2012-10-18

申请号：US13089160

申请日：2011-04-18

Applicant: Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

Inventor： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03K5/15066 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/06

Abstract: An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.

Abstract translation: 实施例是集成电路。 集成电路包括时钟发生器和数据传输线。 时钟发生器产生时钟信号。 至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。 至少部分地通过至少一个时钟信号来触发每个数据传输线。

公开(公告)号：US20120229310A1

公开(公告)日：2012-09-13

申请号：US13045762

申请日：2011-03-11

Applicant: Chih-Hsien Chang

Inventor： Chih-Hsien Chang

IPC: H03M5/00

CPC classification number: G06F13/4072

Abstract: A method includes receiving a first plurality of parallel data; generating a first plurality of encoded data, with each of the first plurality of encoded data same as a respective one of the first plurality of parallel data; and transmitting the first plurality of encoded data simultaneously to a plurality of parallel bus lines, with each of the first plurality of encoded data transmitted by a respective one of the plurality of parallel bus lines. The method further includes receiving a second plurality of parallel data; generating a second plurality of encoded data, with each of the second plurality of encoded data inverted from a respective one of the second plurality of parallel data; and transmitting the second plurality of encoded data simultaneously to the plurality of parallel bus lines, with each of the second plurality of encoded data transmitted by a respective one of the plurality of parallel bus lines.

Abstract translation: 一种方法包括接收第一多个并行数据; 生成第一多个编码数据，其中第一多个编码数据中的每一个与第一多个并行数据中的相应一个相同; 以及将所述第一多个编码数据同时发送到多个并行总线，所述第一多个编码数据中的每一个由所述多个并行总线中的相应一个发送。 该方法还包括接收第二多个并行数据; 产生第二多个编码数据，其中第二多个编码数据中的每一个从第二多个并行数据中的相应一个反转; 以及将所述第二多个编码数据同时发送到所述多个并行总线，其中所述第二多个编码数据中的每一个由所述多个并行总线中的相应一个发送。

公开(公告)号：US20120066559A1

公开(公告)日：2012-03-15

申请号：US12880960

申请日：2010-09-13

Applicant: Jinn-Yeh Chien ,  Chih-Hsien Chang

Inventor： Jinn-Yeh Chien ,  Chih-Hsien Chang

IPC: G06F11/00

CPC classification number: G11C29/12 ,  G11C29/36 ,  G11C29/38

Abstract: System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification.

Abstract translation: 公开了通过使用内置抖动调制电路来测试抖动容限的系统和方法。 一个实施例包括抖动调制电路，发射机，接收机和数据比较单元。 抖动调制电路包括多个数据锁存器，相位选择块和多相时钟发生器。 多相时钟发生器能够产生具有不同相移的多个信号，其中具有来自系统时钟信号的相移的一个信号由相位选择块选择。 所选择的信号通过在多个数据锁存器中注入抖动来改变数据。 抖动污染的数据通过发射机和接收机传输到数据比较单元。 片上测试电路将抖动污染数据与原始数据进行比较，并计算误码率，以确定该半导体器件的抖动容限是否满足规范。

公开(公告)号：US07636660B2

公开(公告)日：2009-12-22

申请号：US11454402

申请日：2006-06-15

Applicant: Chih-Wei Hung ,  Chih-Hsien Chang ,  Hsien-Ming Tsai

Inventor： Chih-Wei Hung ,  Chih-Hsien Chang ,  Hsien-Ming Tsai

IPC: G10L19/00 ,  G10L19/02

CPC classification number: G10L19/0204 ,  G10L19/0212

Abstract: A subband synthesis filtering apparatus for M sets of signals is provided. Each set of signals includes N subband sample signals. The apparatus includes a processor for processing the ith set of signals among the M sets of signals, wherein i is an integer index ranging from 0 to (M−1). The processor includes a DCT converting module and a generating module. The DCT converting module converts the N subband sample signals of the ith set of signals into N converted vectors. If i is an odd number, the (2j−1)th subband sample signal among the N subband sample signals is multiplied by negative one in the converting module, wherein j is an integer index ranging from 1 to (N/2). The generating module generates N pulse code modulation signals based on the N converted vectors.

Abstract translation: 提供了一组用于M组信号的子带合成滤波装置。 每组信号包括N个子带采样信号。 该装置包括处理器，用于处理M组信号中的第i组信号，其中i是从0到（M-1）的整数指数。 处理器包括DCT转换模块和生成模块。 DCT转换模块将第i组信号的N个子带采样信号转换为N个转换矢量。 如果i是奇数，则N个子带采样信号中的第（2j-1）个子带采样信号在转换模块中乘以负1，其中j是范围从1到（N / 2）的整数。 生成模块基于N个转换后的矢量生成N个脉码调制信号。

公开(公告)号：US07502230B2

公开(公告)日：2009-03-10

申请号：US11561012

申请日：2006-11-17

Applicant: Chih-Hsien Chang ,  Kevin Chen

Inventor： Chih-Hsien Chang ,  Kevin Chen

IPC: H05K5/00

CPC classification number: G06F3/023

Abstract: A keyboard, video and mouse (KVM) switch comprises an enclosure; a switching circuit contained within the enclosure; a set of connector ports disposed on the enclosure and electrically coupled to the switching circuit; a set of plugs electrically coupled to the switching circuit, the set of plugs comprising: a video plug disposed on the enclosure for directly coupling to a video port of a first computer system; and at least one peripheral plug attached to the enclosure for coupling to at least one peripheral port of the first computer system; and a cable connector electrically coupled to the switching circuit, for coupling to a second computer system via a detachable cable; wherein the switching circuit switches to operatively couple each connector port to the set of plugs and the cable connector.

Abstract translation: 键盘，视频和鼠标（KVM）开关包括外壳; 包含在所述外壳内的开关电路; 设置在外壳上并电耦合到开关电路的一组连接器端口; 一组插头，电耦合到开关电路，该组插头包括：视频插头，设置在外壳上，用于直接耦合到第一计算机系统的视频端口; 以及附连到所述外壳的至少一个外围插头，用于耦合到所述第一计算机系统的至少一个外围端口; 以及电缆连接器，其电耦合到所述开关电路，用于经由可分离的电缆耦合到第二计算机系统; 其中所述切换电路切换以将每个连接器端口可操作地耦合到所述一组插头和所述电缆连接器。

公开(公告)号：US20080139703A1

公开(公告)日：2008-06-12

申请号：US12029324

申请日：2008-02-11

Applicant: Te-Wei Lee ,  Shu-Pei Chiu ,  Chiu-Yu Yu ,  Tsui-Jung Chang ,  Chih-Hsien Chang

Inventor： Te-Wei Lee ,  Shu-Pei Chiu ,  Chiu-Yu Yu ,  Tsui-Jung Chang ,  Chih-Hsien Chang

IPC: C08L89/00

CPC classification number: A61K9/1271 ,  A61K9/1278 ,  A61K47/62 ,  A61K47/6911 ,  C07K14/6555 ,  Y02P20/55

Abstract: The present invention discloses a method for preparing lipid-spacer-reactive functional group-peptide, wherein the peptide consists of 3 to 16 amino acid residues in which at least one amino acid residue is lysine (Lys), the reactive functional group is a formula of —X—CO—Y—CO—, wherein X represents an oxygen atom or a nitrogen atom, and Y represents C1-6 alkylene which may be interrupted by one or two oxygen or nitrogen atom(s), the spacer is a hydrophilic polymer, and the lipid is phosphatidylethanoaminecarbonyl represented by the formula (I): R1 and R2 are the same or different and individually represent linear or branch C7-30 alkyl or linear or branch C7-30 alkenyl; which is characterized in that the reaction is carried out in a liquid phase and comprises the following steps of (a) firstly protecting Lys amino acid residue in the peptide through a protection group; (b) subsequently reacting the peptide with the lipid-spacer-reactive functional group; and (c) finally removing the protection group from Lys amino acid residue in the peptide.

Abstract translation: 本发明公开了一种制备脂质 - 间隔物反应性官能团肽的方法，其中肽由3至16个氨基酸残基组成，其中至少一个氨基酸残基为赖氨酸（Lys），反应性官能团为式 的-X-CO-Y-CO-，其中X表示氧原子或氮原子，Y表示可被一个或两个氧或氮原子间隔的C 1-6亚烷基（ s），间隔基是亲水性聚合物，并且脂质是由式（I）表示的磷脂酰硫代氨基羰基：R 1和R 2都相同或不同，并且各自代表 直链或支链C 7-30烷基或直链或支链C 7-30链烯基; 其特征在于反应在液相中进行，并包括以下步骤：（a）首先通过保护基保护肽中的Lys氨基酸残基; （b）随后使肽与脂质 - 间隔物反应性官能团反应; 和（c）最后从肽中的Lys氨基酸残基中除去保护基团。

公开(公告)号：US20070083376A1

公开(公告)日：2007-04-12

申请号：US11430702

申请日：2006-05-08

Applicant: Chih-Hsien Chang ,  Chih-Wei Hung ,  Hsien-Ming Tsai

Inventor： Chih-Hsien Chang ,  Chih-Wei Hung ,  Hsien-Ming Tsai

IPC: G10L21/00

CPC classification number: G10L19/0208

Abstract: A synthesis subband filter apparatus is provided. The apparatus is used for processing 18 sets of signals which each includes 32 subband sampling signals in accordance with a specification providing 512 window coefficients. The apparatus includes a processor for processing the 18 sets of signals in sequence. The processor further includes a converting module and a generating module. The converting module is used for converting the 32 subband sampling signals of the set of signals being processed into 32 converted vectors by use of 32-points discrete cosine transform (DCT), and writing the 32 converted vectors into 512 default vectors with a first-in, first-out queue. The generating module is used for generating 32 pulse code modulation (PCM) signals, relative to the set of signals being processed according to a set of synthesis formulae proposed in this invention.

Abstract translation: 提供合成子带滤波器装置。 该装置用于处理根据提供512个窗系数的规范的18组信号，每组信号包括32个子带采样信号。 该装置包括用于依次处理18组信号的处理器。 处理器还包括转换模块和生成模块。 转换模块用于通过使用32点离散余弦变换（DCT）将被处理的信号组的32个子带采样信号转换成32个转换的矢量，并将32个转换的矢量写入512个默认矢量， 在，先出队列。 生成模块用于产生32个脉码调制（PCM）信号，相对于根据本发明中提出的一组合成公式处理的信号集合。

公开(公告)号：US07070329B2

公开(公告)日：2006-07-04

申请号：US10739056

申请日：2003-12-19

Applicant: Chih-Kuang Wang ,  Chih-Hsien Chang

Inventor： Chih-Kuang Wang ,  Chih-Hsien Chang

IPC: F16C29/02

CPC classification number: F16C29/02 ,  F16C33/04

Abstract: A bush and a bearing structure is provided wherein the bush slides along a guiding rod, and the bush is a circular body with an opening to cover the guiding rod over a semicircle. An included angle between the opening and the center of circle of the guiding rod is less than 180 degrees for installing the bush into the bearing structure of a sliding device. The bush is a guiding interface for guiding the sliding device sliding along the guiding rod, and the sliding device can slide along the guiding rod stably.

Abstract translation: 提供了衬套和轴承结构，其中衬套沿着导杆滑动，并且衬套是具有开口的圆形体，以将导杆覆盖在半圆上。 引导杆的开口和圆心之间的夹角小于180度，用于将衬套安装到滑动装置的轴承结构中。 衬套是用于引导滑动装置沿着导杆滑动的引导界面，滑动装置可以沿着导杆稳定地滑动。

公开(公告)号：US20060039513A1

公开(公告)日：2006-02-23

申请号：US10919429

申请日：2004-08-17

Applicant: Ruey-Bin Sheen ,  Chih-Hsien Chang

Inventor： Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: H04L7/00

CPC classification number: H04L7/0338

Abstract: Methods of clock and data recovery (CDR) are provided. An exemplary method comprises extending the eye of the data stream by examining transitions of adjacent samples, detecting whether an island sample exists in each symbol according to the separation of the transitions, and altering the value of the neighboring samples near the island sample to be equal to the island sample.

Abstract translation: 提供了时钟和数据恢复（CDR）的方法。 一种示例性方法包括通过检查相邻样本的转变来扩展数据流的眼睛，根据转换的间隔检测每个符号中是否存在岛样本，以及将岛样本附近的相邻样本的值改变为相等 到岛样品。