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公开(公告)号：US20190067814A1
公开(公告)日：2019-02-28
申请号：US15686630
申请日：2017-08-25
Applicant: Raytheon Company
Inventor： Daniel Thompson , Harry B. Marr , Ian Robinson , Jeffrey Caldwell
Abstract: A system and method of digital beamforming for a monobit phased array radar system includes providing a plurality of monobit analog signals received by at least one antenna to at least one field programmable gate array (FPGA). A plurality of monobit SerDes transceivers within the FPGA convert the plurality of monobit analog signals into a plurality of multibit digital signals, each of the multibit digital signals being modified according to a digital signal conditioning value to calibrate, phase align, and synchronize the digital signals. A digital beam is formed by coherently combining the plurality of digital signals within the FPGA.
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公开(公告)号：US09703991B2
公开(公告)日：2017-07-11
申请号：US14849529
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Won Chon , Harry B. Marr
Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.
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公开(公告)号：US09590760B2
公开(公告)日：2017-03-07
申请号：US14294783
申请日：2014-06-03
Applicant: Raytheon Company
Inventor： Walter B. Schulte, Jr. , John P. Gianvittorio , Harry B. Marr
CPC classification number: H04K3/42 , G01S7/38 , H04L7/0025 , H04L27/2627 , H04L27/34
Abstract: An electronic analog memory system includes at least one analog programmable delay module configured to receive an input radio frequency pulse. The analog programmable delay module generates a time delayed output signal in response to applying at least one time delay to the input radio frequency pulse. A switching module is configured to selectively deliver the time delayed output signal to an output of the electronic analog memory system. The electronic analog memory system further includes an activity detector module configured to determine the amplitude of the input radio frequency pulse. The activity detector module also controls the switching module to deliver the time delayed output signal to the output in response to the at least one amplitude exceeding an amplitude threshold.
Abstract translation: 电子模拟存储器系统包括被配置为接收输入射频脉冲的至少一个模拟可编程延迟模块。 模拟可编程延迟模块响应于对输入射频脉冲施加至少一个时间延迟而产生时间延迟的输出信号。 开关模块被配置为选择性地将时间延迟的输出信号传送到电子模拟存储器系统的输出端。 电子模拟存储器系统还包括被配置为确定输入射频脉冲的幅度的活动检测器模块。 响应于至少一个振幅超过振幅阈值，活动检测器模块还控制切换模块将延时输出信号传送到输出端。
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公开(公告)号：US09543662B2
公开(公告)日：2017-01-10
申请号：US14199126
申请日：2014-03-06
Applicant: Raytheon Company
Inventor： Harry B. Marr , Walter B. Schulte, Jr. , John P. Gianvittorio
IPC: G01S7/03 , G01S13/44 , H01Q25/00 , H01Q3/24 , H01Q3/26 , H04B7/06 , H04B7/08 , G01S7/38 , H01Q15/02
CPC classification number: H01Q25/008 , G01S7/03 , G01S7/38 , G01S13/4409 , H01Q3/2676 , H01Q15/02 , H04B7/0671 , H04B7/0894
Abstract: Embodiments are directed to operating an analog signal processing circuit to emulate a Rotman lens. The analog signal processing circuit applies a plurality of time delays to a plurality of signals associated with a plurality of beam ports. The analog signal processing circuit forms a plurality of output beams for transmission by a plurality of array ports included in an array based on the time delayed signals by summing the time delayed signals. The time delays are based on a direction of transmission of the output beams.
Abstract translation: 实施例涉及操作模拟信号处理电路以模拟Rotman透镜。 模拟信号处理电路对与多个波束端口相关联的多个信号应用多个时间延迟。 模拟信号处理电路通过对时间延迟信号求和来形成多个输出光束，用于通过包括在阵列中的多个阵列端口基于时间延迟的信号进行传输。 时间延迟基于输出光束的传输方向。
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35.发明授权Low-power digital logic using a Boolean logic switched inductor-capacitor (SLC) circuit 有权低功耗数字逻辑使用布尔逻辑开关电感 - 电容（SLC）电路公开(公告)号：US09438233B1
公开(公告)日：2016-09-06
申请号：US14839997
申请日：2015-08-30
Applicant: Raytheon Company
Inventor： Harry B. Marr , Kenneth E. Prager , Julia L. Karl , Daniel Thompson
IPC: H03K19/20 , H03K19/094 , H03K19/00 , H03K19/08
CPC classification number: H03K19/0013 , H03K19/0806
Abstract: A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional switches are used to control the direction of charge flow in a switched-inductor capacitor (SLC) circuit, allowing the inductor to pull charge back-and-forth from one side of the load capacitor to the other to both switch the logical state at the top of the capacitor and to recycle and store the charge in the capacitor itself.
Abstract translation: 低功率数字逻辑架构具有与标准数字逻辑相同的逻辑和电压电平特性。 逻辑开关和一对单向开关用于控制开关电感电容器（SLC）电路中的电荷流动方向，允许电感器从负载电容器的一侧向前拉动负载到另一侧 两者都切换电容器顶部的逻辑状态，并将电荷循环并存储在电容器本身中。
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Patent Agency Ranking
公开(公告)号：US20160248172A1
公开(公告)日：2016-08-25
申请号：US14199126
申请日：2014-03-06
Applicant: Raytheon Company
Inventor： Harry B. Marr , Walter B. Schulte, JR. , John P. Gianvittorio
CPC classification number: H01Q25/008 , G01S7/03 , G01S7/38 , G01S13/4409 , H01Q3/2676 , H01Q15/02 , H04B7/0671 , H04B7/0894
Abstract: Embodiments are directed to operating an analog signal processing circuit to emulate a Rotman lens. The analog signal processing circuit applies a plurality of time delays to a plurality of signals associated with a plurality of beam ports. The analog signal processing circuit forms a plurality of output beams for transmission by a plurality of array ports included in an array based on the time delayed signals by summing the time delayed signals. The time delays are based on a direction of transmission of the output beams.
Abstract translation: 实施例涉及操作模拟信号处理电路以模拟Rotman透镜。 模拟信号处理电路将多个时间延迟应用于与多个波束端口相关联的多个信号。 模拟信号处理电路通过对时间延迟信号求和来形成多个输出光束，用于通过包括在阵列中的多个阵列端口基于时间延迟的信号进行传输。 时间延迟基于输出光束的传输方向。
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公开(公告)号：US20150365185A1
公开(公告)日：2015-12-17
申请号：US14305685
申请日：2014-06-16
Applicant: RAYTHEON COMPANY
Inventor： Daniel Thompson , Harry B. Marr , Nnaemeka Okafor , Chris McLean , Aaron Romulo , Edwin Molina
CPC classification number: H04L27/00 , H04B1/001 , H04B1/0035 , H04J3/02 , H04J3/1694 , H04L27/2652 , H04L27/2657
Abstract: Embodiments are directed to a channelizer architecture configured to provide fully configurable frequency spectrum shaping by: establishing a plurality of parameters of the architecture, receiving an input signal, processing, by the architecture, the input signal in accordance with the plurality of parameters to obtain an output signal, analyzing the output signal to detect an object, and modifying the plurality of parameters to account for at least one dynamic condition associated with the object.
Abstract translation: 实施例涉及一种被配置为通过以下方式提供完全可配置的频谱整形的信道器架构：通过以下方式提供架构的多个参数，接收输入信号，根据该结构处理输入信号，以获得 输出信号，分析输出信号以检测对象，以及修改多个参数以解决与对象相关联的至少一个动态条件。
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公开(公告)号：US20150363359A1
公开(公告)日：2015-12-17
申请号：US14320839
申请日：2014-07-01
Applicant: Raytheon Company
Inventor： Harry B. Marr , Daniel Thompson
CPC classification number: G06F17/142 , H03H17/0213 , H03H17/0248 , H04B1/001
Abstract: A butterfly channelizer includes at least two stages. Each stage includes at least one dual-channel module configured to convert an input time domain signal into a second time domain signal of lower bandwidth. At least one clock is configured to generate a clock signal that drives the at least two stages. A first stage has a first number of dual-channel modules and a second stage following the first stage has a second number of dual-channel modules greater than the first number.
Abstract translation: 蝴蝶渠道化器至少包括两个阶段。 每个级包括至少一个双通道模块，其被配置为将输入时域信号转换为较低带宽的第二时域信号。 至少一个时钟被配置为产生驱动至少两个级的时钟信号。 第一级具有第一数量的双通道模块，并且在第一级之后的第二级具有大于第一数量的第二数量的双通道模块。
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公开(公告)号：US20150349914A1
公开(公告)日：2015-12-03
申请号：US14294783
申请日：2014-06-03
Applicant: Raytheon Company
Inventor： Walter B. Schulte, JR. , John P. Gianvittorio , Harry B. Marr
CPC classification number: H04K3/42 , G01S7/38 , H04L7/0025 , H04L27/2627 , H04L27/34
Abstract: An electronic analog memory system includes at least one analog programmable delay module configured to receive an input radio frequency pulse. The analog programmable delay module generates a time delayed output signal in response to applying at least one time delay to the input radio frequency pulse. A switching module is configured to selectively deliver the time delayed output signal to an output of the electronic analog memory system. The electronic analog memory system further includes an activity detector module configured to determine the amplitude of the input radio frequency pulse. The activity detector module also controls the switching module to deliver the time delayed output signal to the output in response to the at least one amplitude exceeding an amplitude threshold.
Abstract translation: 电子模拟存储器系统包括被配置为接收输入射频脉冲的至少一个模拟可编程延迟模块。 模拟可编程延迟模块响应于对输入射频脉冲施加至少一个时间延迟而产生时间延迟的输出信号。 开关模块被配置为选择性地将时间延迟的输出信号传送到电子模拟存储器系统的输出端。 电子模拟存储器系统还包括被配置为确定输入射频脉冲的幅度的活动检测器模块。 响应于至少一个振幅超过振幅阈值，活动检测器模块还控制切换模块将延时输出信号传送到输出端。
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40.发明申请CIRCUITS AND METHOD TO ENABLE EFFICIENT GENERATION OF DIRECT DIGITAL SYNTHESIZER BASED WAVEFORMS OF ARBITRARY BANDWIDTH 有权直接数字合成器基于波束形成波形的有效生成的电路和方法公开(公告)号：US20140362774A1
公开(公告)日：2014-12-11
申请号：US13910731
申请日：2013-06-05
Applicant: Raytheon Company
Inventor： Harry B. Marr , Daniel Thompson , Julia Karl
IPC: H04K3/00
Abstract: Embodiments of a system and method for providing efficient wideband inverse channelization for direct digital synthesizer based jamming techniques are generally described herein. In some embodiments, metadata associated with a technique for generating a waveform, such as frequency, phase and amplitude parameters, is received. Data select signals and data input are generated based on the received metadata. In-phase and quadrature signals are produced at an output of a first de-multiplexer and a second de-multiplexer, respectively, based on the data select signals and the data input. Frequency modulated signals generated by direct digital synthesizers may be combined in a channel using a separate, distinct channel combiner.
Abstract translation: 本文通常描述用于为基于直接数字合成器的干扰技术提供有效的宽带反向信道化的系统和方法的实施例。 在一些实施例中，接收与用于生成波形的技术（例如频率，相位和幅度参数）相关联的元数据。 基于接收的元数据生成数据选择信号和数据输入。 基于数据选择信号和数据输入，分别在第一解复用器和第二解复用器的输出端产生同相和正交信号。 由直接数字合成器产生的频率调制信号可以使用单独的，不同的信道组合器在信道中组合。
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