公开(公告)号：US20240359698A1

公开(公告)日：2024-10-31

申请号：US18309206

申请日：2023-04-28

Applicant: QUALCOMM Incorporated

Inventor： Amit Aneja ,  Rahul Gulati ,  Sriram Hariharan

IPC: B60W50/04 ,  B60W60/00 ,  G06F8/65

CPC classification number: B60W50/04 ,  B60W60/001 ,  G06F8/65 ,  B60W2050/0016

Abstract: This disclosure provides systems, methods, and devices for vehicles with automated driving systems. In a first aspect, a method of isolation in an automated driving system includes detecting the error in a first domain of the automated driving system, isolating a second domain of the automated driving system from the first domain, maintaining operation of the second domain after isolating the second domain from the first domain, and bypassing, by the second domain, the first domain to transmit notifications to an external controller via a first communication interface. Other aspects and features are also claimed and described.

公开(公告)号：US11545114B2

公开(公告)日：2023-01-03

申请号：US17092165

申请日：2020-11-06

Applicant: QUALCOMM Incorporated

Inventor： Paul Christopher John Wiercienski ,  John Chi Kit Wong ,  Rahul Gulati ,  Gary Arthur Ciambella ,  Sreekanth Modaikkal

IPC: G06F13/00 ,  G09G5/37 ,  G06T1/20 ,  G06F16/23 ,  G06F21/64

Abstract: The present disclosure relates to methods and apparatus for data processing, e.g., a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.

公开(公告)号：US20190197651A1

公开(公告)日：2019-06-27

申请号：US15850907

申请日：2017-12-21

Applicant: QUALCOMM Incorporated

Inventor： Brendon Lewis Johnson ,  Andrew Evan Gruber ,  Jay Chunsup Yun ,  Rahul Gulati ,  Donghyun Kim ,  Alex Kwang Ho Jong

IPC: G06T1/20 ,  G06T1/60 ,  G06F11/10

CPC classification number: G06T1/20 ,  B60K35/00 ,  B60K2370/21 ,  B60R1/00 ,  B60R2300/30 ,  G06F11/1004 ,  G06T1/60 ,  G06T7/001 ,  G06T2207/30108 ,  G09G5/363 ,  G09G2330/08 ,  G09G2330/10 ,  G09G2330/12 ,  G09G2380/10 ,  G09G2380/12

Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.

公开(公告)号：US20190171538A1

公开(公告)日：2019-06-06

申请号：US15832042

申请日：2017-12-05

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  Andrew Evan Gruber ,  Brendon Lewis Johnson ,  Jay Chunsup Yun ,  Donghyun Kim ,  Alex Kwang Ho Jong ,  Anshuman Saxena

IPC: G06F11/22 ,  G06T1/20 ,  G06T15/00 ,  G06F11/07

Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

公开(公告)号：US20190114132A1

公开(公告)日：2019-04-18

申请号：US16127504

申请日：2018-09-11

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Hao Chu ,  Rahul Gulati ,  Robert Hardacker ,  Alex Jong ,  Reza Kakoee ,  Behnam Katibian

IPC: G06F3/14 ,  G09G5/00 ,  B60K35/00

Abstract: Alternative display options for vehicle telltales are disclosed. In one aspect, a fault condition in a telltale is detected, and the telltale is presented through a secondary display system in the vehicle, potentially bypassing any local control unit for the secondary display system. For example, a video telltale may be presented on an infotainment display after detection of a fault in the original telltale. By presenting the telltale in an alternate display, the operator remains informed of sensor conditions in the automobile and may take remedial action to fix the fault as well as any conditions which trigger a telltale.

公开(公告)号：US10061644B2

公开(公告)日：2018-08-28

申请号：US14994078

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Nhon Quach ,  Mainak Biswas ,  Pranjal Bhuyan ,  Jeffrey Shabel ,  Robert Hardacker ,  Rahul Gulati ,  Mattheus Heddes

IPC: G06F12/00 ,  G11C29/52 ,  G06F11/10 ,  G06F12/0888 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F11/1012 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/281 ,  G06F2212/401 ,  G06F2212/466

Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

公开(公告)号：US10012691B1

公开(公告)日：2018-07-03

申请号：US15806212

申请日：2017-11-07

Applicant: QUALCOMM Incorporated

Inventor： Feng Zhou ,  King Tam ,  Shaowen Sun ,  Rahul Gulati ,  Dariusz Krolikowski ,  Peter Koster ,  Serafim Loukas, Jr.

IPC: H04R29/00 ,  G01R31/28

CPC classification number: G01R31/2856 ,  H04R29/001 ,  H04R2499/13

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing a system-on-chip (SoC). The method includes generating data for a plurality of audio channels. The data comprises first data corresponding to a first audio channel and second data corresponding to a second audio channel. The method further includes outputting the first audio channel over a first output port of the SoC for output by a speaker. The method further includes outputting the second audio channel over a second output port. The method further includes looping back the second audio channel from the second output port to a first input port of the SoC as third data. The method further includes comparing the third data to the second data. The method further includes determining if the SoC is operating correctly based on the comparison of the third data to the second data.

公开(公告)号：US20180165814A1

公开(公告)日：2018-06-14

申请号：US15458488

申请日：2017-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  Alex Kwang Ho Jong ,  John Chi Kit Wong ,  Sanjay Gupta ,  Ike Ikizyan

IPC: G06T7/11

CPC classification number: G06T7/11 ,  G06T2207/20021 ,  G06T2207/20104 ,  G06T2207/30252

Abstract: Techniques of this disclosure may include processing one or more regions-of-interest (ROI) of an input image through a model of a display processor, calculating a first data integrity check value on the one or more ROI of the input image after processing through the model, processing the input image by the display processor, calculating a second data integrity check value on the one or more ROI by the display processor after the display processor processes the input image, comparing the first data integrity check value to the second data integrity check value, and generating an interrupt if the comparison indicates that the first data integrity check value and the second data integrity check value do not match.

公开(公告)号：US20170222430A1

公开(公告)日：2017-08-03

申请号：US15012723

申请日：2016-02-01

Applicant: QUALCOMM Incorporated

Inventor： Virendra Bansal ,  Rahul Gulati ,  Pranjal Bhuyan ,  Palkesh Jain

IPC: H02H9/02 ,  H01L23/62 ,  G01R31/02

CPC classification number: H02H9/02 ,  G01R31/025 ,  G01R31/2853 ,  H01L23/62

Abstract: An integrated circuit (IC) is disclosed herein for short-resistant output pin circuitry. In an example aspect, an integrated circuit includes a short-resistant pin and an adjacent pin. The integrated circuit also includes a short-resistant pad that is coupled to the short-resistant pin and an adjacent pad that is coupled to the adjacent pin. The integrated circuit further includes short-resistant circuitry that is coupled to the short-resistant pad and the adjacent pad. The short-resistant circuitry is implemented to detect a short-circuit condition between the short-resistant pin and the adjacent pin and to reduce an effect of the short-circuit condition on the short-resistant pin.

公开(公告)号：US20170094268A1

公开(公告)日：2017-03-30

申请号：US14864348

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  John Chi Kit Wong ,  Pranjal Bhuyan ,  Sanjay Gupta ,  Hemang Jayant Shah

IPC: H04N17/00 ,  B60K35/00

CPC classification number: H04N17/004 ,  B60K35/00 ,  G09G3/006

Abstract: A display processor of a display system may receive an image that includes a test pattern. An input checksum may be associated with the test pattern. Hardware units of the display processor may process the image. The display system may generate an output checksum based at least in part on the test pattern after processing of the image. The display system may detect a fault in the hardware units of the display processor based on determining a difference between the input checksum and the output checksum.