知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

62 records (took 0.023 seconds)

    METHOD TO ESTABLISH OPERATING CONFIGURATION IN A VGMI INTERFACE
    31.
    发明申请
    METHOD TO ESTABLISH OPERATING CONFIGURATION IN A VGMI INTERFACE 审中-公开

    公开(公告)号：US20180357076A1

    公开(公告)日：2018-12-13

    申请号：US16004002

    申请日：2018-06-08

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic WIETFELDT ,  Lalan Jee MISHRA

    IPC: G06F9/445 ,  G06F13/10

    CPC classification number: G06F9/44505 ,  G06F13/102 ,  G06F2009/45579

    Abstract: In an aspect, an apparatus initializes a virtual general-purpose input/output and messaging interface based on at least one of a first mode configuration setting or a first protocol configuration setting. The apparatus is able to communicate with a device over the virtual general-purpose input/output and messaging interface using at least one of the first mode configuration setting or the first protocol configuration setting. The apparatus changes the first mode configuration setting of the virtual general-purpose input/output and messaging interface to a second mode configuration setting and/or changes the first protocol configuration setting of the virtual general-purpose input/output and messaging interface to a second protocol configuration setting. The apparatus communicates with the device over the virtual general-purpose input/output and messaging interface using at least one of the second mode configuration setting or the second protocol configuration setting.

    AUTOMATIC CLOCK RATE SYNCHRONIZATION FOR 1-WIRE RADIO FREQUENCY FRONT-END INTERFACE
    33.
    发明申请
    AUTOMATIC CLOCK RATE SYNCHRONIZATION FOR 1-WIRE RADIO FREQUENCY FRONT-END INTERFACE 有权

    公开(公告)号：US20250062758A1

    公开(公告)日：2025-02-20

    申请号：US18449554

    申请日：2023-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Umesh SRIKANTIAH ,  Richard Dominic WIETFELDT

    IPC: H03K5/24 ,  H03K3/037 ,  H03K3/356

    Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

    VERSATILE CONTROL MESSAGING SCHEME FOR RADIO COEXISTENCE MANAGEMENT
    34.
    发明申请
    VERSATILE CONTROL MESSAGING SCHEME FOR RADIO COEXISTENCE MANAGEMENT 有权

    公开(公告)号：US20220004513A1

    公开(公告)日：2022-01-06

    申请号：US16920150

    申请日：2020-07-02

    Applicant: QUALCOMM Incorporated

    Inventor： Mohit Kishore PRASAD ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

    IPC: G06F13/362 ,  G06F13/42

    Abstract: An apparatus includes an interface circuit adapted to couple the apparatus to a serial bus, a slot counter, and a processor. The slot counter may be configured to monitor a radio frequency coexistence management cycle that includes a plurality of time slots. The processor may be configured to transmit a first datagram through the interface circuit during a first time slot in the plurality of time slots. The apparatus may be uniquely permitted to initiate transactions over the serial bus during the first time slot. The processor may be further configured to participate in an arbitration procedure during a second time slot in the plurality of time slots. More than one device coupled to the serial bus may be permitted to initiate transactions in the second time slot.

    MASTER READ FROM SLAVE OVER PULSE-WIDTH MODULATED HALF-DUPLEX 1-WIRE BUS
    35.
    发明申请
    MASTER READ FROM SLAVE OVER PULSE-WIDTH MODULATED HALF-DUPLEX 1-WIRE BUS 审中-公开

    公开(公告)号：US20200083875A1

    公开(公告)日：2020-03-12

    申请号：US16556835

    申请日：2019-08-30

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

    IPC: H03K7/08 ,  H03K3/0233 ,  H03K5/003

    Abstract: Systems, methods, and apparatus for one wire communication are disclosed. A method performed at a master device includes driving a wire coupling the master device to a slave device from a first voltage to a second voltage, causing a line driver in the master device to present a high impedance to the wire after the wire has been driven to the second voltage, determining that the slave device is communicating a first bit-value when the wire has been driven to the first voltage before a threshold time period has elapsed, determining that the slave device is communicating a second bit-value when the wire is at the second voltage after the threshold time period has elapsed, and driving the wire to transition from the second voltage to the first voltage when the wire is at the second voltage after the threshold time period has elapsed.

    ARCHITECTURE FOR CONSOLIDATING MULTIPLE SOURCES OF LOW-BANDWIDTH DATA OVER A SERIAL BUS
    37.
    发明申请
    ARCHITECTURE FOR CONSOLIDATING MULTIPLE SOURCES OF LOW-BANDWIDTH DATA OVER A SERIAL BUS 审中-公开

    公开(公告)号：US20190227971A1

    公开(公告)日：2019-07-25

    申请号：US16193731

    申请日：2018-11-16

    Applicant: QUALCOMM Incorporated

    Inventor： Helena Deirdre O'SHEA ,  Lalan Jee MISHRA ,  Joaquin ROMERA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A method performed at a first device coupled to a serial bus includes receiving first coexistence information directed to a second device, selecting a communication link to carry the first coexistence information to the second device, generating a first datagram that includes the first coexistence information, transmitting the first datagram to the second device over a point-to-point link in a first mode of operation, and transmitting the first datagram to the second device over a multi-drop serial bus in a second mode of operation. The first datagram may be configured according to a protocol associated with the communication link selected to carry the first coexistence information.

    NON-DESTRUCTIVE OUTSIDE DEVICE ALERTS FOR MULTI-LANE I3C
    38.
    发明申请
    NON-DESTRUCTIVE OUTSIDE DEVICE ALERTS FOR MULTI-LANE I3C 审中-公开

    公开(公告)号：US20190171609A1

    公开(公告)日：2019-06-06

    申请号：US16162536

    申请日：2018-10-17

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Sharon GRAIF

    IPC: G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F13/40

    Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method for transmitting data over a serial bus having multiple data lanes includes providing a plurality of frames, each frame being configured to carry up to a maximum number of data bytes, transmitting a first frame over the serial bus, where the first frame is filled with first data bytes, notifying one or more devices of unavailability of an alert opportunity prior to transmitting the first frame, transmitting a second frame over the serial bus, where the first frame includes second data bytes less in number than the maximum number of data bytes, and notifying the one or more devices that the second frame provides an opportunity to launch an alert after transmission of the second data bytes.

    BIT-INTERLEAVED BI-DIRECTIONAL TRANSMISSIONS ON A MULTI-DROP BUS FOR TIME-CRITICAL DATA EXCHANGE
    39.
    发明申请
    BIT-INTERLEAVED BI-DIRECTIONAL TRANSMISSIONS ON A MULTI-DROP BUS FOR TIME-CRITICAL DATA EXCHANGE 审中-公开

    公开(公告)号：US20190171595A1

    公开(公告)日：2019-06-06

    申请号：US16184284

    申请日：2018-11-08

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

    IPC: G06F13/362 ,  G06F13/42 ,  G06F1/10

    Abstract: Systems, methods, and apparatus for optimizing bus latency using bit-interleaved bidirectional transmission on a serial bus are described. A method performed at a device coupled to a serial bus includes pairing with a second device in a transaction to be conducted over the serial bus, transmitting a first data bit to the second device over a data line of the serial bus in a first part of each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus, and receiving a second data bit transmitted by the second device on the data line in a second part of each cycle. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.

    CLOCK LINE DRIVING FOR SINGLE-CYCLE DATA OVER CLOCK SIGNALING AND PRE-EMPTION REQUEST IN A MULTI-DROP BUS
    40.
    发明申请
    CLOCK LINE DRIVING FOR SINGLE-CYCLE DATA OVER CLOCK SIGNALING AND PRE-EMPTION REQUEST IN A MULTI-DROP BUS 审中-公开

    公开(公告)号：US20190171589A1

    公开(公告)日：2019-06-06

    申请号：US16167193

    申请日：2018-10-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/161 ,  G06F13/376 ,  G06F13/4291 ,  G06F2213/0008 ,  G06F2213/0064

    Abstract: Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

Patent Agency Ranking