公开(公告)号：US20150145143A1

公开(公告)日：2015-05-28

申请号：US14132098

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/522 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US20140145347A1

公开(公告)日：2014-05-29

申请号：US13792486

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。