公开(公告)号：US20150162065A1

公开(公告)日：2015-06-11

申请号：US14276452

申请日：2014-05-13

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill KIM ,  Jungwon SUH ,  Xiangyu DONG

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G06F12/0207 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

Abstract: A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

Abstract translation: 存储器刷新控制技术允许基于外部1×刷新率的灵活的内部刷新率，并允许基于外部1×刷新率跳过强存储器行的刷新周期。 存储器控制器通过从刷新地址计数器读取刷新地址，从弱地址表读取弱地址并且至少部分地基于与弱地址组合的下一个比特序列产生下一个弱地址值来执行存储器刷新。 存储器控制器将刷新地址与弱地址和下一个弱地址值进行比较。 基于比较，存储器控制器在跳过刷新周期，刷新刷新地址，刷新弱地址以及刷新刷新地址和弱地址之间进行选择。

公开(公告)号：US20150121006A1

公开(公告)日：2015-04-30

申请号：US14062558

申请日：2013-10-24

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu DONG ,  Xiaochun ZHU ,  Jungwon SUH

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/60 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1084 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C2207/2245 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

Abstract translation: 读取和写入电阻式存储器高速缓存的方法包括接收写入命令并将写入命令分成多个写入子命令。 该方法还包括在执行下一个写入子命令之前接收读取命令并执行读取命令。

公开(公告)号：US20150016203A1

公开(公告)日：2015-01-15

申请号：US14148515

申请日：2014-01-06

Applicant: QUALCOMM Incorporated

Inventor： Deepti Vijayalakshmi SRIRAMAGIRI ,  Jungwon SUH ,  Xiangyu DONG

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40611

Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

Abstract translation: 一种刷新动态随机存取存储器（DRAM）的方法包括：检测在DRAM存储体的开放子阵列内的DRAM存储体的行的DRAM的打开页面。 该方法还包括当DRAM存储体的目标刷新行位于DRAM存储体的打开子阵列内时，向DRAM存储体的目标刷新行延迟发出刷新命令。

公开(公告)号：US20140379978A1

公开(公告)日：2014-12-25

申请号：US14242769

申请日：2014-04-01

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill KIM ,  Xiangyu DONG ,  Jungwon SUH

IPC: G11C11/401 ,  G11C11/406

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4065

Abstract: A memory refresh method within a memory controller includes checking a first retention state corresponding to a first memory address and a second retention state corresponding to a second memory address. The memory refresh method also includes performing a refresh operation on a row corresponding to the second memory address when the second retention state indicates a weak retention state. The first memory address corresponds to a refresh counter address, and the second memory address corresponds to a complementary address of the refresh counter address.

Abstract translation: 存储器控制器内的存储器刷新方法包括检查对应于第一存储器地址的第一保留状态和对应于第二存储器地址的第二保留状态。 所述存储器刷新方法还包括当所述第二保持状态指示弱保持状态时，对与所述第二存储器地址相对应的行执行刷新操作。 第一存储器地址对应于刷新计数器地址，并且第二存储器地址对应于刷新计数器地址的补充地址。