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公开(公告)号：US20210201433A1
公开(公告)日：2021-07-01
申请号：US16728591
申请日：2019-12-27
Applicant: QUALCOMM Incorporated
Inventor： Balaji CALIDAS , Joshua Walter Kelly , Avinash Seetharamaiah , Jonnala Gadda Nagendra Kumar , Hitendra Mohan Gangani
Abstract: Methods, systems, and devices for processing are described. A device may parse a set of layers of a deep neural network. The set of layers may be associated with a set of machine learning operations of the deep neural network. The device may determine one or more layer parameters based on the determined set of layers. In some aspects, the device may determine an execution time associated with executing a shader dispatch based on the one or more layer parameters. The device may batch the shader dispatch to a command buffer based on the execution time and process the command buffer based on the batching. The device may determine a target execution time based on an assembly time associated with the command buffer, a processing time associated with the command buffer, a frequency level associated with processing the command buffer, the one or more layer parameters, or some combination thereof.
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公开(公告)号：US20200027189A1
公开(公告)日：2020-01-23
申请号：US16042172
申请日：2018-07-23
Applicant: QUALCOMM Incorporated
Inventor： Jonnala Gadda Nagendra Kumar , Andrew Yelder , Jian Liang , Avinash Seetharamaiah
Abstract: Methods, systems, and devices for dependency detection of a graphical processor unit (GPU) workload at a device are described. The method relates to generating a resource packet for a first GPU workload of a set of GPU workloads, the resource packet including a list of resources, identifying a first resource from the list of resources, retrieving a GPU address from a first memory location associated with the first resource, determining whether a dependency of the first resource exists between the first GPU workload and a second GPU workload from the set of GPU workloads based on the retrieving of the GPU address, and processing, when the dependency exists, the first resource after waiting for a duration to lapse.
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公开(公告)号：US10282813B2
公开(公告)日：2019-05-07
申请号：US15895652
申请日：2018-02-13
Applicant: QUALCOMM Incorporated
Inventor： Murat Balci , Avinash Seetharamaiah , Christopher Paul Frascati , Jonnala Gadda Nagendra Kumar , Colin Christopher Sharp , David Rigel Garcia Garcia
Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.
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公开(公告)号：US20190087198A1
公开(公告)日：2019-03-21
申请号：US15711422
申请日：2017-09-21
Applicant: QUALCOMM Incorporated
Inventor： Christopher Paul Frascati , Rajakumar Govindaram , Hitendra Mohan Gangani , Murat Balci , Lida Wang , Avinash Seetharamaiah , Mansoor Aftab , Rajdeep Ganguly , Josiah Vivona
Abstract: A method for camera processing using a camera application programming interface (API) is described. A processor executing the camera API may be configured to receive instructions that specify a use case for a camera pipeline, the use case defining at least one or more processing engines of a plurality of processing engines for processing image data with the camera pipeline, wherein the plurality of processing engines includes one or more of fixed-function image signal processing nodes internal to a camera processor and one or more processing engines external to the camera processor. The processor may be further configured to route image data to the one or more processing engines specified by the instructions, and return the results of processing the image data with the one or more processing engines to the application.
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公开(公告)号：US10078883B2
公开(公告)日：2018-09-18
申请号：US14958911
申请日：2015-12-03
Applicant: QUALCOMM Incorporated
Inventor： Siddhartha Baral , Avinash Seetharamaiah , Christopher Paul Frascati
CPC classification number: G06T1/60 , G06T1/20 , G06T15/80 , G06T2210/12 , G06T2210/52
Abstract: This disclosure is directed to graphics data storage. A graphics processing unit (GPU) may determine pixels of a tile for which the GPU generated graphics data during the rendering of the tile. The GPU may store the generated graphics data in a local memory, and use the information of the pixels of the tile for which the GPU generated graphics data to limit the amount of graphics data stored in the local memory that the GPU is to write to an external memory.
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Patent Agency Ranking
公开(公告)号：US20180165788A1
公开(公告)日：2018-06-14
申请号：US15895652
申请日：2018-02-13
Applicant: QUALCOMM Incorporated
Inventor： Murat Balci , Avinash Seetharamaiah , Christopher Paul Frascati , Jonnala Gadda Nagendra Kumar , Colin Christopher Sharp , David Rigel Garcia Garcia
CPC classification number: G06T1/20 , G06T1/60 , G06T11/40 , G09G5/00 , G09G2330/021
Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.
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公开(公告)号：US09928565B2
公开(公告)日：2018-03-27
申请号：US14691358
申请日：2015-04-20
Applicant: QUALCOMM Incorporated
Inventor： Murat Balci , Avinash Seetharamaiah , Christopher Paul Frascati , Jonnala gadda Nagendra Kumar , Colin Christopher Sharp , David Rigel Garcia Garcia
CPC classification number: G06T1/20 , G06T1/60 , G06T11/40 , G09G5/00 , G09G2330/021
Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.
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公开(公告)号：US09799088B2
公开(公告)日：2017-10-24
申请号：US14465371
申请日：2014-08-21
Applicant: QUALCOMM Incorporated
Inventor： Christopher Paul Frascati , Murat Balci , Avinash Seetharamaiah , Maurice Franklin Ribble , Hitendra Mohan Gangani
CPC classification number: G06T1/20 , G06F9/451 , G06T1/60 , G06T15/005 , G09G5/18
Abstract: In an example, a method for rendering graphics data includes receiving a plurality of commands associated with a plurality of render targets, where the plurality of commands are received in an initial order. The method also includes determining an execution order for the plurality of commands including reordering one or more of the plurality of commands in a different order than the initial order based on data dependencies between commands. The method also includes executing the plurality of commands in the determined execution order.
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公开(公告)号：US09530245B2
公开(公告)日：2016-12-27
申请号：US13708118
申请日：2012-12-07
Applicant: QUALCOMM Incorporated
Inventor： Christopher Paul Frascati , Avinash Seetharamaiah , Joseph Blankenship
IPC: G06T15/80 , G06T17/20 , G06T11/00 , G06T1/60 , G06T15/83 , G06T17/10 , G06T1/20 , G06T7/40 , G06T15/04 , G06F9/445
CPC classification number: G06T15/80 , G06F9/445 , G06F9/44594 , G06T1/20 , G06T1/60 , G06T7/40 , G06T11/00 , G06T15/04 , G06T15/83 , G06T17/10 , G06T17/20
Abstract: This disclosure describes techniques for packing multiple shader programs of a common shader program type onto a graphics processing unit (GPU). The techniques may include, for example, causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time. In addition, various techniques for evicting shader programs from an on-chip shader program instruction memory are described.
Abstract translation: 本公开描述了将共同着色器程序类型的多个着色器程序打包到图形处理单元（GPU）上的技术。 这些技术可以包括例如使得共同着色器程序类型的多个着色器程序被加载到图形处理器的片上着色器程序指令存储器中，使得多个着色器程序中的每个着色器程序驻留在 片上着色器程序指令存储器在公共时间点。 此外，描述了用于从片上着色器程序指令存储器驱逐着色器程序的各种技术。
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公开(公告)号：US09483861B2
公开(公告)日：2016-11-01
申请号：US13841584
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Christopher Paul Frascati , Avinash Seetharamaiah , Andrew Evan Gruber
CPC classification number: G06T15/005
Abstract: This disclosure describes techniques for using bounding regions to perform tile-based rendering with a graphics processing unit (GPU) that supports an on-chip, tessellation-enabled graphics rendering pipeline. Instead of generating binning data based on rasterized versions of the actual primitives to be rendered, the techniques of this disclosure may generate binning data based on a bounding region that encompasses one or more of the primitives to be rendered. Moreover, the binning data may be generated based on data that is generated by at least one tessellation processing stage of an on-chip, tessellation-enabled graphics rendering pipeline that is implemented by the GPU. The techniques of this disclosure may, in some examples, be used to improve the performance of an on-chip, tessellation-enabled GPU when performing tile-based rendering without sacrificing the quality of the resulting rendered image.
Abstract translation: 本公开描述了使用边界区域来执行基于瓦片的渲染的技术，该图形处理单元（GPU）支持片上，镶嵌的图形渲染流水线。 基于要渲染的实际原语的光栅化版本而不是生成合并数据，本公开的技术可以基于包含要呈现的一个或多个基元的边界区域来生成合并数据。 此外，可以基于由GPU实现的片上，镶嵌使能的图形呈现流水线的至少一个镶嵌处理阶段生成的数据来生成合并数据。 在一些示例中，本公开的技术可以用于在不牺牲所得到的渲染图像的质量的情况下执行基于图块的渲染时，提高片上，镶嵌功能的GPU的性能。
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