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公开(公告)号：US12046310B2
公开(公告)日：2024-07-23
申请号：US17859873
申请日：2022-07-07
发明人： Wu-Der Yang
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure extending along a first direction and electrically connected to a first transistor, a second gate structure extending along the first direction and electrically connected to a second transistor, a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, and a first conductive element extending along the second direction and disposed on the first active region. The first conductive element is electrically connected to the first active region. The first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed. The first gate structure and the first active region form a first fuse element, and the second gate structure and the first active region form a second fuse element.
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公开(公告)号：US12021017B2
公开(公告)日：2024-06-25
申请号：US17492093
申请日：2021-10-01
发明人： Wu-Der Yang
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31 , H01L23/498
CPC分类号： H01L23/49838 , H01L23/3128 , H01L24/48 , H01L2224/48227
摘要： The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor die, a package substrate and bonding wires. The semiconductor die has I/O pads arranged at an active side. The package substrate is provided with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and has an opening penetrating through the package substrate. The I/O pads are overlapped with the opening. A width of the opening at the second side of the package substrate is greater than a width of the opening at the first side of the package substrate. The bonding wires connect the I/O pads to the second side of the package substrate through the opening of the package substrate.
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公开(公告)号：US11876067B2
公开(公告)日：2024-01-16
申请号：US17451158
申请日：2021-10-18
发明人： Wu-Der Yang
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/49 , H01L24/09 , H01L24/20 , H01L24/85 , H01L25/0657 , H01L2224/09515 , H01L2224/4903 , H01L2224/49111 , H01L2225/0651 , H01L2924/30107
摘要： A semiconductor package includes a package substrate, a semiconductor chip and a plurality of bonding wires. The package substrate includes a connection pad. The semiconductor chip is disposed over the package substrate and includes a chip pad, a bonding pad, and a redistribution layer. The bonding pad is closer to a periphery of the semiconductor chip than the chip pad. The redistribution layer is connected between the chip pad and the bonding pad. The bonding wires are connected in parallel between the connection pad and the bonding pad.
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公开(公告)号：US11769562B2
公开(公告)日：2023-09-26
申请号：US17517794
申请日：2021-11-03
发明人： Wu-Der Yang
CPC分类号： G11C17/18 , G11C17/16 , H01L21/4853 , H01L22/12 , H01L24/48 , H01L2224/48157
摘要： The present application discloses an electronic fuse control circuit, a semiconductor device and a method for forming a semiconductor device including an electronic fuse control circuit. The electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, an operation switch unit, resistor selection pads, and bonding option units. The fuse element includes a first terminal coupled to the program voltage pad, and a second terminal. The operation switch unit forms an electrical connection between the second terminal of the fuse element and a ground terminal during a program operation, and forms an electrical connection between the second terminal of the fuse element and an input terminal of the latch during a read operation. Each of the bonding option units includes a resistor and a selection switch coupled in series between the input terminal of the latch and a resistor selection pad.
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公开(公告)号：US11677403B1
公开(公告)日：2023-06-13
申请号：US17880669
申请日：2022-08-04
发明人： Wu-Der Yang
CPC分类号： H03L7/0812 , H03L7/085 , H03K19/0002 , H03K19/20
摘要： A delay lock loop circuit includes a receiver, a delay line circuit, a clock signal generator and a phase detecting circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal according to the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal with a delay indication signal. The clock signal generator generates an output clock signal according to the delayed clock signal. The phase detecting circuit generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal according to a digital value of the detection result.
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公开(公告)号：US11508729B2
公开(公告)日：2022-11-22
申请号：US17031477
申请日：2020-09-24
发明人： Wu-Der Yang
IPC分类号： H01L27/108 , H01L27/08 , H01L49/02 , H01L23/00
摘要： The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.
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公开(公告)号：US11502070B2
公开(公告)日：2022-11-15
申请号：US16933974
申请日：2020-07-20
发明人： Wu-Der Yang
IPC分类号： H01L25/18 , H01L23/367 , H01L23/467
摘要： A electronic module includes a printed circuit board (PCB) substrate, a controller substrate, a controller, a memory device, and a heat spreader. The controller is disposed on the controller substrate. The memory device is disposed on the PCB substrate. The heat spreader is disposed on the controller and the memory device, in which the heat spreader has a first portion on the controller and a second portion on the memory device, and the heat spreader has a first opening between the first portion and the second portion.
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公开(公告)号：US11469216B2
公开(公告)日：2022-10-11
申请号：US16832305
申请日：2020-03-27
发明人： Wu-Der Yang , Chun-Huang Yu
IPC分类号： H01L25/065 , H01L23/498 , H01L21/56 , H01L23/00 , H01L25/00 , H01L23/31
摘要： The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.
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公开(公告)号：US20220101935A1
公开(公告)日：2022-03-31
申请号：US17643188
申请日：2021-12-08
发明人： Wu-Der Yang
摘要： The present disclosure provides a method of testing a testing device with a ground noise. The method includes coupling a device under test in series between a source and a ground in an automatic test equipment, coupling a ground bounce generator in series between the device under test and the ground, coupling the testing device to the device under test, providing a current by the source through the device under test and the ground bounce generator, controlling the ground bounce generator to generate the ground noise, and collecting a performance result of the testing device in the automatic test equipment.
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公开(公告)号：US11069646B2
公开(公告)日：2021-07-20
申请号：US16583289
申请日：2019-09-26
发明人： Wu-Der Yang
摘要： The disclosure provides a printed circuit board structure. The printed circuit board structure includes a printed circuit board, a semiconductor chip, a first pad, a second pad, a conductive wire, and a third pad. The semiconductor chip is disposed on the printed circuit board. The first pad is disposed on the semiconductor chip. The second pad is disposed on the printed circuit board. The conductive wire electrically connects the first pad and the second pad. The third pad is disposed between the first pad and the second pad. The conductive wire has a portion located on the third pad.
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