公开(公告)号：US10412390B2

公开(公告)日：2019-09-10

申请号：US15641224

申请日：2017-07-04

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Tung-Hsing Wu ,  Li-Heng Chen ,  Ting-An Lin ,  Yi-Hsin Huang ,  Chung-Hua Tsai ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Yung-Chang Chang

IPC: H04N19/13 ,  H04N19/70 ,  H04N19/44 ,  H04N21/23 ,  H04N21/84 ,  H04N19/124 ,  H04N19/172 ,  H04N19/18 ,  H04N19/174 ,  H04N21/2365 ,  H04N21/2665 ,  H04N21/2343 ,  H04N21/845

Abstract: A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.

公开(公告)号：US10356438B2

公开(公告)日：2019-07-16

申请号：US15578191

申请日：2016-06-03

Applicant: MEDIATEK INC.

Inventor： Tzu-Der Chuang ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Ching-Yeh Chen ,  Yu-Chen Sun ,  Yu-Wen Huang

IPC: H04N19/593 ,  H04N19/563 ,  H04N19/513 ,  H04N19/70

Abstract: In order to overcome the issue caused by a decoded block vector (BV) pointing to a reference block overlapping with an unavailable area, various methods are disclosed. According to one method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by padding from neighboring available pixels. The padding can be done in the horizontal direction and then the vertical direction. The padding may also done in the vertical direction first and then horizontal direction. In another method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by using previous decoded pixels in the unavailable area. A pre-defined value may also be used for the unavailable area.

公开(公告)号：US10244248B2

公开(公告)日：2019-03-26

申请号：US15438774

申请日：2017-02-22

Applicant: MEDIATEK INC.

Inventor： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N19/436 ,  H04N19/61

Abstract: A residual processing circuit has a single-path pipeline and a single-path controller. The single-path pipeline has an inverse scan (IS) circuit, an inverse quantization (IQ) circuit and an inverse transform (IT) circuit arranged to process a current non-zero residual data block in a pipeline manner. The current non-zero residual data block is at least a portion of a transform unit. The single-path controller controls pipelined processing of the current non-zero residual data block at the single-path pipeline. The single-path controller instructs the IS circuit to start IS processing of a next non-zero residual data block before the IT circuit finishes a first half of IT processing of the current non-zero residual data block.

公开(公告)号：US10230948B2

公开(公告)日：2019-03-12

申请号：US15422425

申请日：2017-02-01

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Han-Liang Chou ,  Yung-Chang Chang

IPC: H04N19/10 ,  H04N19/15 ,  H04L1/00 ,  H04N19/423 ,  H04N19/436 ,  H04N19/182

Abstract: A video transmitting system includes a source buffer, a video encoder, a bitstream buffer, and a transmitting circuit. The source buffer receives pixel data of pixels of a video frame. The video encoder retrieve pixel data of a portion of the pixels of the video frame from the source buffer, and starts encoding the pixel data of the portion of the pixels before pixel data of a last pixel of the video frame is received by the source buffer. The bitstream buffer receives a network abstraction layer (NAL) stream from the video encoder, wherein the NAL stream is generated by encoding the pixel data of the portion of the pixels. The transmitting circuit retrieves the NAL stream from the bitstream buffer, and starts outputting the NAL stream before the pixel data of the last pixel of the video frame is encoded by the video encoder.

公开(公告)号：US10205957B2

公开(公告)日：2019-02-12

申请号：US14997691

申请日：2016-01-18

Applicant: MediaTek Inc.

Inventor： Chia-Yun Cheng ,  Sheng-Jen Wang ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N19/174 ,  H04N19/91 ,  H04N19/42 ,  H04N19/70

Abstract: An apparatus for multi-standard bin decoding in a video decoder for decoding two video coded in two different video coding standards is disclosed. The apparatus includes a first bin decoder to decode one or more first bin strings, a second bin decoder to decode one or more second bin strings, a standard change control module coupled to the first bin decoder and the second bin decoder and a system controller coupled to the standard change control module, the first bin decoder and the second bin decoder. The standard change control module or the system controller selects either a next slice or picture to be decoded by the first bin decoder or the second bin decoder based on one or more control parameters including the decoding time information.

公开(公告)号：US20180018999A1

公开(公告)日：2018-01-18

申请号：US15646095

申请日：2017-07-11

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: G11B20/10 ,  H04N21/434 ,  H04N21/44 ,  H04N21/4363 ,  H04N19/423 ,  G09G5/393 ,  H04N21/435

CPC classification number: G11B20/10527 ,  G09G5/393 ,  G09G2360/127 ,  G11B2020/10666 ,  G11B2020/1074 ,  G11B2020/10768 ,  G11B2020/10787 ,  G11B2020/10796 ,  H04N19/423 ,  H04N21/4341 ,  H04N21/4343 ,  H04N21/435 ,  H04N21/43635 ,  H04N21/43637 ,  H04N21/44004

Abstract: A video processing system has a storage device, an audio/video demultiplexing circuit, and a video decoder. The storage device has a bitstream buffer that is a ring buffer. The audio/video demultiplexing circuit receives an input data, and performs an audio/video demultiplexing operation upon the input data to write data of a video bitstream into the ring buffer. The video decoder fetches data of the video bitstream from the ring buffer, and performs a video decoding operation upon the fetched data of the video bitstream.

公开(公告)号：US09762906B2

公开(公告)日：2017-09-12

申请号：US14179540

申请日：2014-02-12

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Huei-Min Lin ,  Yung-Chang Chang

IPC: H04N19/436 ,  H04N19/82 ,  H04N19/86 ,  H04N19/51

CPC classification number: H04N19/865 ,  H04N19/436 ,  H04N19/51 ,  H04N19/82

Abstract: A method and apparatus for deblocking process using multiple processing units are disclosed. The video image is divided into at least two regions. The in-loop filter is applied to block boundaries associated with said at least two regions using multiple processing units. The in-loop filter is re-applied to one or more second block boundaries adjacent to region edge between two regions after applying the in-loop filter to the first block boundaries adjacent to the region edge. Furthermore, at least a first portion of said applying the in-loop filter to the first block boundaries and a second portion of said applying the in-loop filter to the second block boundaries are performed concurrently. The multiple processing units may correspond to multiple processing cores within one processor chip.

公开(公告)号：US20170244967A1

公开(公告)日：2017-08-24

申请号：US15439964

申请日：2017-02-23

Applicant: MEDIATEK INC.

Inventor： Sheng-Jen Wang ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04N19/13 ,  G06F13/28 ,  H04N19/70

CPC classification number: H04N19/13 ,  G06F13/28 ,  H04N19/42 ,  H04N19/70 ,  H04N19/91

Abstract: A video processing apparatus includes an external storage device, a hardware entropy engine, and a software execution engine. The hardware entropy engine performs entropy processing of a current picture, and further outputs count information to the external storage device during the entropy processing of the current picture. When loaded and executed by the software execution engine, a software program instructs the software execution engine to convert the count information into count table contents, and generate a count table in the external storage device according to at least the count table contents. The count table is referenced to apply a backward adaptation to a probability table that is selectively used by the hardware entropy engine to perform entropy processing of a next picture.

公开(公告)号：US20170019679A1

公开(公告)日：2017-01-19

申请号：US15202538

申请日：2016-07-05

Applicant: MEDIATEK INC.

Inventor： Sheng-Jen Wang ,  Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang ,  Hao-Chun Chung ,  Yu-Cheng Chu ,  Shen-Kai Chang

IPC: H04N19/50 ,  H04N19/176 ,  H04N19/91 ,  H04N19/70 ,  H04N19/44

CPC classification number: H04N19/91 ,  H04N19/423 ,  H04N19/433

Abstract: A hybrid video decoding apparatus has a hardware entropy decoder and a storage device. The hardware entropy decoder performs hardware entropy decoding to generate an entropy decoding result of a picture. The storage device has a plurality of storage areas allocated to buffer a plurality of entropy-decoded partial data, respectively, and is further arranged to store position information indicative of storage positions of the entropy-decoded partial data in the storage device. The entropy-decoded partial data are derived from the entropy decoding result of the picture, and are associated with a plurality of portions of the picture, respectively.

Abstract translation: 混合视频解码装置具有硬件熵解码器和存储装置。 硬件熵解码器执行硬件熵解码以产生图像的熵解码结果。 存储装置具有分配用于分别缓冲多个熵解码的部分数据的多个存储区域，并且还被布置为将表示熵解码的部分数据的存储位置的位置信息存储在存储装置中。 熵解码的部分数据从图像的熵解码结果导出，并分别与图像的多个部分相关联。

公开(公告)号：US20160191922A1

公开(公告)日：2016-06-30

申请号：US14979546

申请日：2015-12-28

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/146 ,  H04N19/127 ,  H04N19/172

CPC classification number: H04N19/423 ,  G06F5/065 ,  G06F12/0811 ,  G06F2205/067 ,  G06F2212/283 ,  H04N19/127 ,  H04N19/172 ,  H04N19/436 ,  H04N19/44

Abstract: A method, apparatus and computer readable medium storing a corresponding computer program for decoding a video bitstream based on multiple decoder cores are disclosed. In one embodiment of the present invention, the method arranges multiple decoder cores to decode one or more frames from a video bitstream using mixed level parallel decoding. The multiple decoder cores are arranged into groups of multiple decoder cores for parallel decoding one or more frames by using one group of multiple decoder cores for said one or more frames, wherein each group of multiple decoder cores comprises one or more decoder cores. The number of frames to be decoded in the mixed level parallel decoding or which frames to be decoded in the mixed level parallel decoding is adaptively determined.

Abstract translation: 公开了一种基于多个解码器核存储用于解码视频比特流的相应计算机程序的方法，装置和计算机可读介质。 在本发明的一个实施例中，该方法使用混合电平并行解码来设置多个解码器核来从视频比特流解码一个或多个帧。 多个解码器核被布置成多个解码器核心组，用于通过对于所述一个或多个帧使用一组多个解码器核来并行解码一个或多个帧，其中每组多个解码器核心包括一个或多个解码器核心。 在混合电平并行解码中要解码的帧的数量或在混合电平并行解码中要解码的帧被自适应地确定。