公开(公告)号：US06362086B1

公开(公告)日：2002-03-26

申请号：US09397763

申请日：1999-09-15

Applicant: Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

Inventor： Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

IPC: H01L214763

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal suicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multilayer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

公开(公告)号：US06291868B1

公开(公告)日：2001-09-18

申请号：US09031407

申请日：1998-02-26

Applicant: Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

Inventor： Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

IPC: H01L2976

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/2807 ,  H01L21/32105

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract translation: 用于半导体器件的导电结构包括多层结构。 第一层包括含硅的材料，例如多晶硅和锗锗。 在第一层上形成阻挡层，阻挡层包括金属硅化物或金属硅化物氮化物。 在阻挡层上形成顶部导电层。 顶部导电层可以包括金属或金属硅化物。 可以进行选择性氧化以减少包含多层结构的结构中所选材料的氧化量，例如多层导电结构。 选择性氧化在单晶片快速热处理系统中进行，其中使用包括氢的所选择的环境来确保所选择的材料如钨或金属氮化物的低氧化。

公开(公告)号：US5930106A

公开(公告)日：1999-07-27

申请号：US678729

申请日：1996-07-11

Applicant: Scott J. Deboer ,  Klaus F. Schuegraf ,  Ronald A. Weimer ,  Randhir P. S. Thakur

Inventor： Scott J. Deboer ,  Klaus F. Schuegraf ,  Ronald A. Weimer ,  Randhir P. S. Thakur

IPC: H01L21/02 ,  H01L21/8242 ,  H01G4/008 ,  H01G4/06

CPC classification number: H01L28/40 ,  H01L27/10852

Abstract: An exemplary implementation of the present invention includes a capacitor for a dynamic random access memory cell having a first plate; a second plate; and a dielectric layer interposed between said first and second plates, with the dielectric layer being dominated by electrode-limited conduction, which includes tantalum pentoxide and silicon nitride, or a combination of the two. In a preferred implementation, one of the two capacitor plates is formed from a silicon-germanium layer, the second plate is formed from a metal and the dielectric layer is formed from tantalum pentoxide.

公开(公告)号：US08294192B2

公开(公告)日：2012-10-23

申请号：US13168902

申请日：2011-06-24

Applicant: Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

Inventor： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28273 ,  H01L29/511

Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract translation: 闪存集成电路及其制造方法。 栅极堆叠包括直接与硅层接触的初始氧化物层，在其间界定氧化物 - 硅界面。 另外的氧化物材料沿着氧化硅 - 硅界面基本均匀地形成。 因此在界面处的多晶硅晶界被蚀刻后钝化。 界面可以形成在隧道氧化物和浮动栅极之间，钝化晶界可以减少擦除变化。 在稀释蒸汽氧化中，上储存电介质层中的氧化物得到增强。 薄氧化物层用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US20110133268A1

公开(公告)日：2011-06-09

申请号：US13024903

申请日：2011-02-10

Applicant: Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

Inventor： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

IPC: H01L29/792

CPC classification number: G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

Abstract translation: 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

公开(公告)号：US07915126B2

公开(公告)日：2011-03-29

申请号：US11706177

申请日：2007-02-14

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.

Abstract translation: 一些实施方案包括在形成非挥发性记忆体中使用聚硅氮烷的方法。 存储器单元可以是多级单元（MLC）。 聚硅氮烷可以通过热加工转化为氮化硅，二氧化硅或氮氧化硅，并暴露于含有氧和氮的一种或两种的环境中。 所述方法可以包括使用聚硅氮烷形成非易失性存储单元的电荷捕获层。 所述方法可以或另外包括使用聚硅氮烷形成非易失性存储单元的隔间介电材料。 一些实施例包括形成NAND存储器阵列的存储单元的方法。

公开(公告)号：US07906393B2

公开(公告)日：2011-03-15

申请号：US10767298

申请日：2004-01-28

Applicant: Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  Cem Basceri ,  David J. Kubista

Inventor： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Kevin L. Beaman ,  Ronald A. Weimer ,  Cem Basceri ,  David J. Kubista

IPC: H01L21/8242

CPC classification number: H01L28/40 ,  H01L21/3141 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/84

Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.

Abstract translation: 本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。 一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。 可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层 至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。 第二导电层可以与介电层接触并具有不大于约的厚度。

公开(公告)号：US20090004794A1

公开(公告)日：2009-01-01

申请号：US12204603

申请日：2008-09-04

Applicant: Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

Inventor： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28273 ,  H01L29/511

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract translation: 本发明提供一种闪速存储器集成电路及其制造方法。 该方法包括蚀刻包括与硅层直接接触的初始氧化物层的栅极堆叠，在其之间限定氧化物 - 硅界面。 通过将蚀刻的栅极堆叠暴露于升高的温度和稀释的蒸气环境，沿着氧化物 - 硅界面基本均匀地形成附加的氧化物材料。 因此在界面处的多晶硅晶界被蚀刻后钝化。 在优选实施例中，在隧道氧化物和浮动栅极之间形成界面，并且由于沿着晶界的增强的电荷转移而使晶界钝化从而减小了擦除可变性。 同时，在稀释蒸汽氧化中，上部存储介质层（氧化物 - 氧化物 - 氧化物或ONO）中的氧化物被增强。 通过在蚀刻之前在氮化物层的任一侧上生长薄的氧化物层，并且通过在蚀刻后通过暴露的侧壁进行稀释的蒸汽氧化来增强氧化物层，从而可以完全保守热预算。 薄氧化物层，如初始隧道氧化物，用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US20080194066A1

公开(公告)日：2008-08-14

申请号：US11706177

申请日：2007-02-14

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.

Abstract translation: 一些实施方案包括在形成非挥发性记忆体中使用聚硅氮烷的方法。 存储器单元可以是多级单元（MLC）。 聚硅氮烷可以通过热加工转化为氮化硅，二氧化硅或氮氧化硅，并暴露于含有氧和氮的一种或两种的环境中。 所述方法可以包括使用聚硅氮烷形成非易失性存储单元的电荷捕获层。 所述方法可以或另外包括使用聚硅氮烷形成非易失性存储单元的隔间介电材料。 一些实施例包括形成NAND存储器阵列的存储单元的方法。

公开(公告)号：US07282439B2

公开(公告)日：2007-10-16

申请号：US11216914

申请日：2005-08-31

Applicant: Ronald A. Weimer ,  John T. Moore

Inventor： Ronald A. Weimer ,  John T. Moore

IPC: H01L21/4763 ,  H01L21/311

CPC classification number: H01L21/0276 ,  H01L21/02126 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3145 ,  H01L21/3146 ,  H01L21/3148 ,  H01L21/31604 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S257/90 ,  Y10S438/97

Abstract: The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies. One particular disclosed film is an anti-reflective coating, and a method of formation thereof.

Abstract translation: 本发明涉及包含硅，氧和碳的薄膜以及集成电路技术中的薄膜的使用，例如电容器结构，DRAM结构，半导体材料组件，蚀刻工艺以及用于形成电容器，DRAM和半导体材料组件的方法。 一种特别公开的膜是抗反射涂层及其形成方法。