公开(公告)号：US09793096B2

公开(公告)日：2017-10-17

申请号：US14668174

申请日：2015-03-25

申请人： LAM RESEARCH CORPORATION

发明人： Hu Kang ,  Adrien LaVoie ,  Shankar Swaminathan ,  Jun Qian ,  Chloe Baldasseroni ,  Frank Pasquale ,  Andrew Duvall ,  Ted Minshall ,  Jennifer Petraglia ,  Karl Leeser ,  David Smith ,  Sesha Varadarajan ,  Edward Augustyniak ,  Douglas Keil

IPC分类号： H01J37/32 ,  C23C16/505 ,  C23C16/455 ,  C23C16/40 ,  C23C16/34

CPC分类号： H01J37/3244 ,  C23C16/345 ,  C23C16/402 ,  C23C16/405 ,  C23C16/45565 ,  C23C16/505 ,  C23C16/509 ,  H01J37/32568 ,  H01J37/32623

摘要： A substrate processing system for depositing film on a substrate includes a processing chamber defining a reaction volume. A showerhead includes a stem portion having one end connected adjacent to an upper surface of the processing chamber. A base portion is connected to an opposite end of the stem portion and extends radially outwardly from the stem portion. The showerhead is configured to introduce at least one of process gas and purge gas into the reaction volume. A plasma generator is configured to selectively generate RF plasma in the reaction volume. An edge tuning system includes a collar and a parasitic plasma reducing element that is located around the stem portion between the collar and an upper surface of the showerhead. The parasitic plasma reducing element is configured to reduce parasitic plasma between the showerhead and the upper surface of the processing chamber.

公开(公告)号：US20170140968A1

公开(公告)日：2017-05-18

申请号：US15074808

申请日：2016-03-18

申请人： Lam Research Corporation

发明人： Yukinori Sakiyama ,  Edward Augustyniak ,  Douglas Keil

IPC分类号： H01L21/683 ,  C23C16/458 ,  H01L21/263

CPC分类号： H01L22/20 ,  C23C16/45565 ,  C23C16/4585 ,  C23C16/4586 ,  C23C16/50 ,  C23C16/509 ,  C23C16/52 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/32137 ,  H01J37/32715 ,  H01J37/32935 ,  H01J37/3299 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/263 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67201 ,  H01L21/683 ,  H01L22/12

摘要： An apparatus for supporting a wafer during a plasma processing operation includes a pedestal configured to have bottom surface and a top surface and a column configured to support the pedestal at a central region of the bottom surface of the pedestal. An electrical insulating layer is disposed over the top surface of the pedestal.An electrically conductive layer is disposed over the top surface of the electrical insulating layer. At least three electrically conductive support structures are distributed on the electrically conductive layer. The at least three support structures are configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer. An electrical connection extends from the electrically conductive layer to connect with a positive terminal of a direct current power supply at a location outside of the pedestal.