公开(公告)号：US20130092989A1

公开(公告)日：2013-04-18

申请号：US13273012

申请日：2011-10-13

Applicant: Yu-Wei Ting ,  Kuo-Ching Huang

Inventor： Yu-Wei Ting ,  Kuo-Ching Huang

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L29/78

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

公开(公告)号：US20130070396A1

公开(公告)日：2013-03-21

申请号：US13239359

申请日：2011-09-21

Applicant: Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

Inventor： Che-Hung Huang ,  Kuo-Ching Huang ,  Chih-Ling Chien

IPC: H05K5/02

CPC classification number: G06F1/1624 ,  H04M1/0237 ,  H04M1/0239

Abstract: A hand-held device includes a first body, a second body, a sliding module, and a guiding module. The sliding module is disposed between the first body and the second body, so that the second body is able to be slid on a two-dimensional plane relative to the first body. The guiding module includes a first guiding part and a second guiding part. The first guiding part is fixed to the first body. The second guiding part is fixed to the second body and coupled to the first guiding part. Besides, the second guiding part is able to be moved along a guiding path relative to the first guiding part, so that the second body is able to be slid along the guiding path on the two-dimensional plane relative to the first body.

Abstract translation: 手持式装置包括第一主体，第二主体，滑动模块和引导模块。 滑动模块设置在第一主体和第二主体之间，使得第二主体能够相对于第一主体在二维平面上滑动。 引导模块包括第一引导部分和第二引导部分。 第一个引导部分固定在第一个身体。 第二引导部分固定到第二主体并且联接到第一引导部分。 此外，第二引导部能够相对于第一引导部沿着引导路径移动，使得第二主体能够相对于第一主体沿着二维平面上的引导路径滑动。

公开(公告)号：US07595999B2

公开(公告)日：2009-09-29

申请号：US11766204

申请日：2007-06-21

Applicant: Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

Inventor： Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

IPC: H05K7/06

CPC classification number: H05K1/0271 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit.

Abstract translation: 信息处理系统电路板具有通过其形成的开口，其靠近集成电路到电路板的耦合点。 开口处理集成电路到电路板的耦合点处的应力，以减少在电路板变形期间对耦合点的损坏的风险，例如当电路板耦合到底盘或当部件被按压时 进入电路板。 在一个实施例中，在BSA集成电路的对角相对的角上形成矩形开口。 在替代实施例中，在集成电路的选定角处形成变化形状的开口，例如槽或弯曲槽。

公开(公告)号：US20080079050A1

公开(公告)日：2008-04-03

申请号：US11528405

申请日：2006-09-28

Applicant: Kuo-Chyuan Tzeng ,  C.Y. Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chih-Yang Chang

Inventor： Kuo-Chyuan Tzeng ,  C.Y. Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chih-Yang Chang

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10894

Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件的示例性实施例包括在其中形成有多个隔离结构的衬底，其在衬底上限定第一和第二区域。 晶体管分别形成在第一和第二区域中的衬底的一部分上，其中第二区域中的晶体管仅在与衬底的漏极区相邻的衬底中仅形成一个凹坑掺杂区域。 第一电介质层形成在衬底上，覆盖形成在第一和第二区域中的晶体管。 通过第一介电层形成多个第一接触插塞，分别在第二区域中电连接晶体管的源极区域和漏极区域。 在第一电介质层上形成第二电介质层，其中形成有电容器，其中电容器电连接第一接触插塞之一。

公开(公告)号：US06860828B2

公开(公告)日：2005-03-01

申请号：US10065206

申请日：2002-09-25

Applicant: Kuo-Ching Huang

Inventor： Kuo-Ching Huang

IPC: F16H7/08 ,  F16H7/22

CPC classification number: F16H7/08 ,  F16H2007/0804 ,  F16H2007/0808

Abstract: A belt tension adjustment apparatus and an optical scanner using the same. The belt tension adjustment apparatus includes a plate spring and/or a tension spring. Utilizing the elasticity of the plate spring or the elastic forces provided by the plate spring and the tension spring, a section of the transmission belt bends to produce a tension in the belt. With the belt tension adjustment apparatus, belt tension in the transmission belt can be easily adjusted and hence the belt can be easily mounted or dismounted from the belt wheels during installation, maintenance or adjustment.

Abstract translation: 皮带张力调节装置和使用其的光学扫描仪。 带张力调节装置包括板簧和/或张力弹簧。 利用板簧的弹性或由板簧和张力弹簧提供的弹力，传动带的一部分弯曲以在带中产生张力。 通过皮带张力调节装置，可以容易地调节传动带中的皮带张力，因此在安装，维护或调整过程中，皮带可以方便地从皮带轮上安装或卸下。

公开(公告)号：US06833578B1

公开(公告)日：2004-12-21

申请号：US10733216

申请日：2003-12-11

Applicant: Kuo-Chi Tu ,  Chun-Yao Chen ,  Huey-Chi Chu ,  Chung-Wei Chang ,  Tien-Lu Lin ,  Kuo-Ching Huang ,  Wen-Cheng Chen ,  Tsung-Hsun Huang ,  Hsiao-Hui Tseng

Inventor： Kuo-Chi Tu ,  Chun-Yao Chen ,  Huey-Chi Chu ,  Chung-Wei Chang ,  Tien-Lu Lin ,  Kuo-Ching Huang ,  Wen-Cheng Chen ,  Tsung-Hsun Huang ,  Hsiao-Hui Tseng

IPC: H01L27108

CPC classification number: H01L28/57 ,  H01L27/11 ,  H01L28/90

Abstract: A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.

Abstract translation: 一种存储单元，包括具有插入第一和第二垂直设置的电极的介电层的电容器，位于电容器上方的绝缘衬垫，以及通过电容器的晶体管栅极延伸。 间隔件将电容器电极之一的端部与晶体管栅极延伸部隔离。 在一个实施例中，间隔件包括构造成接合包括电容器电极之一和绝缘衬里的端部的第二非平面轮廓的第一非平面轮廓。

公开(公告)号：US06638813B1

公开(公告)日：2003-10-28

申请号：US10059825

申请日：2002-01-29

Applicant: Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

Inventor： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11

Abstract: A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.

Abstract translation: 已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。 首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。 接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。 接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。 湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。 多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

公开(公告)号：US06433665B1

公开(公告)日：2002-08-13

申请号：US09839702

申请日：2001-04-23

Applicant: Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

Inventor： Kuo-Ching Huang ,  Jin Yuan Lee ,  Tse-Liang Ying

IPC: H01F500

Abstract: An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

公开(公告)号：US06420226B1

公开(公告)日：2002-07-16

申请号：US10020753

申请日：2001-12-12

Applicant: Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

Inventor： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

IPC: H01L218244

CPC classification number: H01L27/105 ,  H01L27/11 ,  H01L28/91 ,  H01L29/66181

Abstract: A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

Abstract translation: 已经开发了用于单晶体管，RAM单元中的埋层叠层电容器结构的制造工艺。 该方法特征在于通过选择性干法蚀刻工艺形成形成在氧化硅填充的浅沟槽形状的顶部的自对准的环形存储节点开口。 选择性干蚀刻方法与随后的选择性湿法蚀刻程序结合，在环形存储节点开口和相邻的半导体顶表面的接合处产生半导体衬底的裸露部分，允许在该区域中产生重掺杂区域。 当在环形存储节点结构中形成存储节点结构时，以及在重掺杂区域上覆盖时，重掺杂区域的存在将节点与衬底电阻降低。

公开(公告)号：US06351016B1

公开(公告)日：2002-02-26

申请号：US09389630

申请日：1999-09-03

Applicant: Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

Inventor： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC: H01L2976

CPC classification number: H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

Abstract: A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了埋地接触点。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。