Abstract:
Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.
Abstract:
Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.
Abstract:
In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.
Abstract:
In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.
Abstract:
A method, system, and/or computer program product for dynamic array masking is provided. Dynamic array masking includes, during execution of computer instructions that access a cache memory, detecting an error condition in a portion of the cache memory. The portion of the cache memory contains an array macro. Dynamic array masking, during the execution of the computer instructions that access a cache memory, further includes dynamically setting mask bits to indicate the error condition in the portion of the cache memory and preventing subsequent writes to the portion of the cache memory in accordance with the dynamically set mask bits. Embodiments also include evicting cache entries from the portion of the cache memory. This evicting can include performing a cache purge operation for the cache entries corresponding to the dynamically set mask bits.
Abstract:
A multi-boundary address protection range is provided to prevent key operations from interfering with a data move performed by a dynamic memory relocation (DMR) move operation. Any key operation address that is within the move boundary address range gets rejected back to the hypervisor. Further, logic exists across a set of parallel slices to synchronize the DMR move operation as it crosses a protected boundary address range.
Abstract:
A method, system, and/or computer program product for dynamic array masking is provided. Dynamic array masking includes, during execution of computer instructions that access a cache memory, detecting an error condition in a portion of the cache memory. The portion of the cache memory contains an array macro. Dynamic array masking, during the execution of the computer instructions that access a cache memory, further includes dynamically setting mask bits to indicate the error condition in the portion of the cache memory and preventing subsequent writes to the portion of the cache memory in accordance with the dynamically set mask bits. Embodiments also include evicting cache entries from the portion of the cache memory. This evicting can include performing a cache purge operation for the cache entries corresponding to the dynamically set mask bits.
Abstract:
Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.
Abstract:
Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
Abstract:
System refresh in a cache memory that includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory and activating a refresh request at the centralized refresh controller based on generating the RTIM pulse. The refresh request is associated with a single cache memory bank of the cache memory. A refresh grant is received and transmitted to a bank controller. The bank controller is associated with and localized at the single cache memory bank of the cache memory.