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    TEMPORALLY AMORTIZED SUPERSAMPLING USING A MIXED PRECISION CONVOLUTIONAL NEURAL NETWORK
    31.
    发明申请
    TEMPORALLY AMORTIZED SUPERSAMPLING USING A MIXED PRECISION CONVOLUTIONAL NEURAL NETWORK 有权

    公开(公告)号：US20230066626A1

    公开(公告)日：2023-03-02

    申请号：US17516112

    申请日：2021-11-01

    Applicant: Intel Corporation

    Inventor： SungYe Kim ,  Karthik Vaidyanathan ,  Gabor Liktor ,  Manu Mathew Thomas

    IPC: G06T3/40 ,  G06T3/00 ,  G06T15/50 ,  G06T19/20 ,  G06N3/04

    Abstract: One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling operation via a mixed precision convolutional neural network, the set of processing resources including circuitry configured to receive, at an input block of a neural network model, history data, velocity data, and current frame data, pre-process the history data, velocity data, and current frame data to generate pre-processed data, provide the pre-processed data to a feature extraction network of the neural network model, process the pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, and generate an output image via an output block of the neural network model via direct reconstruction or kernel prediction.

    Ray tracing apparatus and method for memory access and register operations
    32.
    发明授权
    Ray tracing apparatus and method for memory access and register operations 有权

    公开(公告)号：US11367243B2

    公开(公告)日：2022-06-21

    申请号：US17108774

    申请日：2020-12-01

    Applicant: Intel Corporation

    Inventor： Carsten Benthin ,  Ingo Wald ,  Gabor Liktor ,  Johannes Guenther ,  Elmoustapha Ould-Ahmed-Vall

    IPC: G06T15/06 ,  G06T15/00 ,  G06T9/00 ,  G06T9/40

    Abstract: An apparatus and method for performing BVH compression and decompression concurrently with stores and loads, respectively. For example, one embodiment comprises: bounding volume hierarchy (BVH) construction circuitry to build a BVH based on a set of input primitives, the BVH comprising a plurality of uncompressed coordinates; traversal/intersection circuitry to traverse one or more rays through the BVH and determine intersections with the set of input primitives using the uncompressed coordinates; store with compression circuitry to compress the BVH including the plurality of uncompressed coordinates to generate a compressed BVH with compressed coordinates and to store the compressed BVH to a memory subsystem; and load with decompression circuitry to decompress the BVH including the compressed coordinates to generate a decompressed BVH with the uncompressed coordinates and to load the decompressed BVH with uncompressed coordinates to a cache and/or a set of registers accessible by the traversal/intersection circuitry.

    Speculative execution of hit and intersection shaders on programmable ray tracing architectures
    35.
    发明授权
    Speculative execution of hit and intersection shaders on programmable ray tracing architectures 有权

    公开(公告)号：US10909741B2

    公开(公告)日：2021-02-02

    申请号：US16236176

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

    IPC: G06T15/06 ,  G06T15/00 ,  G06T1/60

    Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

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