公开(公告)号：US20220093546A1

公开(公告)日：2022-03-24

申请号：US17025181

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L49/02 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US20220093517A1

公开(公告)日：2022-03-24

申请号：US17025166

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid ,  Randy B. Osborne ,  Van H. Le

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/49

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.

公开(公告)号：US11222856B2

公开(公告)日：2022-01-11

申请号：US16721603

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L21/48 ,  H01L49/00 ,  H01L23/498 ,  H01H61/01 ,  H01H49/00 ,  H01H61/00 ,  H01L23/00

Abstract: Embodiments may relate to a package substrate that includes a signal line and a ground line. The package substrate may further include a switch communicatively coupled with the ground line. The switch may have an open position where the switch is communicatively decoupled with the signal line, and a closed position where the switch is communicatively coupled with the signal line. Other embodiments may be described or claimed.

公开(公告)号：US20210358855A1

公开(公告)日：2021-11-18

申请号：US17388964

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US11101205B2

公开(公告)日：2021-08-24

申请号：US16564168

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US20210202404A1

公开(公告)日：2021-07-01

申请号：US16728278

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/34

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.

公开(公告)号：US20210202403A1

公开(公告)日：2021-07-01

申请号：US16728127

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L23/498 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.

公开(公告)号：US20210193519A1

公开(公告)日：2021-06-24

申请号：US16721243

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.

公开(公告)号：US20210193518A1

公开(公告)日：2021-06-24

申请号：US16721235

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.

公开(公告)号：US10998272B2

公开(公告)日：2021-05-04

申请号：US16573943

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic interposer may be formed using organic material layers, while allowing for the fabrication of high density interconnects within the electronic interposer without the use of embedded silicon bridges. This is achieved by forming the electronic interposer in three sections, i.e. an upper section, a lower section and a middle section. The middle section may be formed between the upper section and the lower section, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section, and wherein conductive routes within the middle section have a higher density than conductive routes within the upper section and the lower section.