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    Adjustable Precision for Multi-Stage Compute Processes
    32.
    发明申请
    Adjustable Precision for Multi-Stage Compute Processes 审中-公开

    公开(公告)号：US20200042287A1

    公开(公告)日：2020-02-06

    申请号：US16052218

    申请日：2018-08-01

    申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    发明人： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  Sergey Serebryakov ,  John Paul Strachan

    IPC分类号： G06F7/483 ,  G06N3/063 ,  G06N3/08

    摘要： Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.

    Dynamic Thread Mapping
    34.
    发明申请
    Dynamic Thread Mapping 审中-公开

    公开(公告)号：US20190034239A1

    公开(公告)日：2019-01-31

    申请号：US16073573

    申请日：2016-04-27

    申请人： Hewlett Packard Enterprise Development LP

    发明人： Qiong Cai ,  Charles Johnson ,  Paolo Faraboschi

    IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/52 ,  G06F12/0811

    摘要： In one example, a central processing unit (CPU) with dynamic thread mapping includes a set of multiple cores each with a set of multiple threads. A set of registers for each of the multiple threads monitors for in-flight memory requests the number of loads from and stores to at least a first memory interface and a second memory interface by each respective thread. The second memory interface has a greater latency than the first memory interface. The CPU further has logic to map and migrate each thread to respective CPU cores where the number of cores accessing only one of the at least first and second memory interfaces is maximized.

    Floating point data set compression
    39.
    发明授权
    Floating point data set compression 有权

    公开(公告)号：US11018692B2

    公开(公告)日：2021-05-25

    申请号：US16942293

    申请日：2020-07-29

    申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    发明人： Anirban Nag ,  Naveen Muralimanohar ,  Paolo Faraboschi

    IPC分类号： H03M7/30 ,  H03M7/24

    摘要： Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.