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31.发明授权公开(公告)号：US12106209B1
公开(公告)日：2024-10-01
申请号：US18401718
申请日：2024-01-02
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim
Abstract: A method for evaluating artificial neural network (ANN) model's processing performance comprising selecting a type and a number of at least one neural processing unit (NPU) for processing performance evaluation for a user, selecting at least one of a plurality of compilation options for an artificial neural network (ANN) model to be processed by the at least one NPU which is selected, uploading the ANN model and at least one evaluation dataset to be processed by the at least one NPU which is selected, compiling the ANN model according to the at least one of the plurality of compilation options which is selected, and reporting a processing performance by processing the ANN model on the at least one NPU which is selected.
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公开(公告)号：US12040040B2
公开(公告)日：2024-07-16
申请号：US18193351
申请日：2023-03-30
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim , Jeong Kyun Yim
IPC: G11C29/00 , G05B19/418 , G06F11/26 , G11C29/10
CPC classification number: G11C29/78 , G05B19/41875 , G06F11/26 , G11C29/10 , G05B2219/32368 , G05B2219/45031
Abstract: A neural processing unit (NPU) for testing a component during runtime is provided. The NPU may include a plurality of functional components including a first functional component and a second functional component. At least one of the plurality of functional components may be driven for calculation of an artificial neural network. Another one of the plurality of functional components may be selected as a component under test (CUT). A scan test may be performed on the at least one functional component selected as the CUT. A tester for detecting a defect of an NPU is also provided. The tester may include a component tester configured to communicate with at least one functional component of the NPU, select the at least one functional component as a CUT, and perform a scan test for the selected CUT.
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公开(公告)号：US20240220153A1
公开(公告)日：2024-07-04
申请号：US18602955
申请日：2024-03-12
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06N3/063
Abstract: According to an example of the present disclosure, a system is provided. A system may include a main memory including a dynamic memory cell electrically coupled to a bitline and a word line, and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell.
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公开(公告)号：US11990203B2
公开(公告)日：2024-05-21
申请号：US17849667
申请日：2022-06-26
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim , Jeong Kyun Yim
IPC: G06F11/26 , G05B19/418 , G11C29/00 , G11C29/10
CPC classification number: G11C29/78 , G05B19/41875 , G06F11/26 , G11C29/10 , G05B2219/32368 , G05B2219/45031
Abstract: A neural processing unit (NPU) is capable of testing a component of the NPU in a running system, i.e., during runtime. The NPU includes a plurality of functional components, each of which includes an electronic circuit; at least one wrapper connected to at least one of the functional components; and an in-system component tester (ICT). The ICT performs a selection of one of the at least one functional component, in an idle state, as a component under test (CUT) and performs a test, via the at least one wrapper, of the selected functional component. The ICT may monitor states of the plurality of the functional components via the at least one wrapper, stop the test based on a detection of a collision due to an access to the selected functional component, and return a connection of the selected functional component to the at least one wrapper according to the stop.
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公开(公告)号：US11977916B2
公开(公告)日：2024-05-07
申请号：US17431152
申请日：2020-12-31
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim
CPC classification number: G06F9/4881 , G06F15/80
Abstract: A neural network processing unit (NPU) includes a processing element array, an NPU memory system configured to store at least a portion of data of an artificial neural network model processed in the processing element array, and an NPU scheduler configured to control the processing element array and the NPU memory system based on artificial neural network model structure data or artificial neural network data locality information.
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Patent Agency Ranking
36.发明授权公开(公告)号：US11972137B2
公开(公告)日：2024-04-30
申请号：US17514028
申请日：2021-10-29
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06N3/063
Abstract: A system for an artificial neural network (ANN) includes a main memory including a dynamic memory cell electrically coupled to a bit line and a word line; and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell. The main memory may be configured to selectively omit the restoration operation during the read operation of the dynamic memory cell by controlling a voltage applied to the word line. The memory controller may be further configured to determine whether to perform the restoration operation by determining whether data stored in the dynamic memory cell is reused. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.
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公开(公告)号：US11954586B2
公开(公告)日：2024-04-09
申请号：US18459605
申请日：2023-09-01
Applicant: DEEPX CO., LTD.
Inventor： Seong Jin Lee , Jung Boo Park , Lok Won Kim
CPC classification number: G06N3/063
Abstract: A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.
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公开(公告)号：US11893783B2
公开(公告)日：2024-02-06
申请号：US18317728
申请日：2023-05-15
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim , Ha Joon Yu
CPC classification number: G06V10/82 , G06V10/7715
Abstract: A neural processing unit (NPU) for decoding video or feature map is provided. The NPU may comprise at least one processing element (PE) to perform an inference using an artificial neural network. The at least one PE may be configured to receive and decode data included in a bitstream. The data included in the bitstream may comprise data of a base layer. Alternatively, the data included in the bitstream may comprise data of the base layer and data of at least one enhancement layer. The data of the base layer included in the bitstream may include a first feature map. The data of the at least one enhancement layer included in the bitstream may include a second feature map.
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公开(公告)号：US11893477B2
公开(公告)日：2024-02-06
申请号：US18353404
申请日：2023-07-17
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim , Jung Boo Park , Seong Jin Lee
CPC classification number: G06N3/063
Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.
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公开(公告)号：US11861486B2
公开(公告)日：2024-01-02
申请号：US17985257
申请日：2022-11-11
Applicant: DEEPX CO., LTD.
Inventor： Lok Won Kim , Quang Hieu Vo
IPC: G06N3/063
CPC classification number: G06N3/063
Abstract: A neural processing unit of a binarized neural network (BNN) as a hardware accelerator is provided, for the purpose of reducing hardware resource demand and electricity consumption while maintaining acceptable output precision. The neural processing unit may include: a first block configured to perform convolution by using a binarized feature map with a binarized weight; and a second block configured to perform batch-normalization on an output of the first block. A register having a particular size may be disposed between the first block and the second block. Each of the first block and the second block may include one or more processing engines. The one or more processing engines may be connected in a form of pipeline.
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