公开(公告)号：US20180365095A1

公开(公告)日：2018-12-20

申请号：US15663455

申请日：2017-07-28

Applicant: Cisco Technology, Inc.

Inventor： John Thomas Monk ,  Kartik Mohanram ,  Ramana Rao Kompella ,  Sundar Iyer

IPC: G06F11/07

Abstract: Systems, methods, and computer-readable media for fault code aggregation across application-centric dimensions. In an example embodiment, a system obtains respective fault codes corresponding to one or more network devices in a network and maps the one or more network devices and/or the respective fault codes to respective logical policy entities defined in a logical policy model of the network, to yield fault code mappings. The system aggregates the one or more of the fault code mappings along respective logical policy dimensions in the network to yield an aggregation of fault codes across respective logical policy dimensions and, based on the aggregation, presents, for each of the respective logical policy dimensions, one or more hardware-level errors along the respective logical policy dimension.

公开(公告)号：US09390212B2

公开(公告)日：2016-07-12

申请号：US14702971

申请日：2015-05-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC: G11C11/00 ,  G06F17/50 ,  G11C11/419

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

公开(公告)号：US09280464B2

公开(公告)日：2016-03-08

申请号：US14730696

申请日：2015-06-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0292 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/657

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. This allows the memory system to both store and read data in the same cycle with no conflicts.

Abstract translation: 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。 这允许存储器系统在相同周期内存储和读取数据，而不会发生冲突。

公开(公告)号：US20150357030A1

公开(公告)日：2015-12-10

申请号：US14831008

申请日：2015-08-20

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell.

Abstract translation: 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。 为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。 双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。 单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。 通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。

公开(公告)号：US20150234950A1

公开(公告)日：2015-08-20

申请号：US14702971

申请日：2015-05-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC: G06F17/50 ,  G11C11/419

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Abstract translation: 现代数字集成电路中通常需要多端口存储器电路来存储数据。 多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。 多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。 然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。 公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

公开(公告)号：US11824728B2

公开(公告)日：2023-11-21

申请号：US17112854

申请日：2020-12-04

Applicant: Cisco Technology, Inc.

Inventor： Divjyot Sethi ,  Chandra Nagarajan ,  Advait Dixit ,  John Thomas Monk ,  Gabriel Cheukbun Ng ,  Ramana Rao Kompella ,  Sundar Iyer

IPC: H04L41/14 ,  H04W24/04 ,  H04W24/06 ,  H04L41/5019 ,  H04L43/50 ,  G06F9/455 ,  H04L43/55

CPC classification number: H04L41/145 ,  H04L41/5019 ,  H04W24/04 ,  H04W24/06 ,  G06F9/45533 ,  H04L43/50 ,  H04L43/55

Abstract: Systems, methods, and computer-readable media for emulating a state of a network environment for purposes of re-executing a network assurance appliance in the emulated state of the network environment. In some embodiments, a method can include receiving snapshot data for a network environment corresponding to a specific time in the network environment and including network events occurring in the network environment generated by a network assurance appliance. A state of the network environment at the specific time can be emulated using the snapshot data to create an emulated state of the network environment. Subsequently, the network assurance appliance can be re-executed in the emulated state of the network environment corresponding to the specific time and the network assurance appliance can be debugged outside of the network environment based on re-execution of the network assurance appliance in the emulated state of the network environment.

公开(公告)号：US11563645B2

公开(公告)日：2023-01-24

申请号：US17153831

申请日：2021-01-20

Applicant: Cisco Technology, Inc.

Inventor： Advait Dixit ,  Ramana Rao Kompella ,  Kartik Mohanram ,  Sundar Iyer ,  Shadab Nazar ,  Chandra Nagarajan

IPC: G06F15/173 ,  H04L41/16 ,  H04L41/14 ,  H04L41/5022 ,  H04L41/5054 ,  H04L41/0631 ,  H04L41/0866 ,  H04L41/142 ,  H04L41/147 ,  H04L41/12 ,  H04L41/0893

Abstract: Systems, methods, and computer-readable media for receiving one or more models of network intents, comprising a plurality of contracts between providers and consumers, each contract containing entries with priority values. Each contract is flattened into a listing of rules and a new priority value is calculated. The listing of rules encodes the implementation of the contract between the providers and the consumers. Each entry is iterated over and added to a listing of entries if it is not already present. For each rule, the one or more entries associated with the contract from which the rule was flattened are identified, and for each given entry a flat rule comprising the combination of the rule and the entry is generated, wherein a flattened priority is calculated based at least in part on the priority value of the given one of given entry and the priority value of the rule.

公开(公告)号：US20210377123A1

公开(公告)日：2021-12-02

申请号：US17394285

申请日：2021-08-04

Applicant: Cisco Technology, Inc.

Inventor： Chetan Narsude ,  Gaurav Gupta ,  Shadab Nazar ,  Pavan Mamillapalli ,  Sundar Iyer

IPC: H04L12/24 ,  H04L12/26 ,  G06F11/34

Abstract: Aspects of the technology provide solutions for determining a time period (“epoch”) required to monitor or analyze a tenant network. Some implementations of the technology include a process for making automatic epoch determinations, which includes steps for identifying one or more network parameters for a tenant network, analyzing the tenant network using the network parameters to discover one or more configuration settings of the tenant network, and determining a first epoch for the tenant network, the first epoch corresponding with a period of time to complete analysis of the tenant network using the network parameters. In some aspects, the process can further include steps for generating a tenant profile for the tenant network, the tenant profile based on the network parameters, the first epoch, and the one or more configuration settings of the tenant network. Systems and machine-readable media are also provided.

公开(公告)号：US11178009B2

公开(公告)日：2021-11-16

申请号：US16786349

申请日：2020-02-10

Applicant: Cisco Technology, Inc.

Inventor： Kartik Mohanram ,  Chandra Nagarajan ,  Sundar Iyer ,  Shadab Nazar ,  Ramana Rao Kompella

IPC: H04L12/24 ,  H04L12/26

Abstract: Systems, methods, and computer-readable media for static network policy analysis for a network. In one example, a system obtains a logical model based on configuration data stored in a controller on a software-defined network, the logical model including a declarative representation of respective configurations of objects in the software-defined network, the objects including one or more endpoint groups, bridge domains, contexts, or tenants. The system defines rules representing respective conditions of the objects according to a specification corresponding to the software-defined network, and determines whether the respective configuration of each of the objects in the logical model violates one or more of the rules associated with that object. When the respective configuration of an object in the logical model violates one or more of the rules, the system detects an error in the respective configuration associated with that object.

公开(公告)号：US11121927B2

公开(公告)日：2021-09-14

申请号：US16704874

申请日：2019-12-05

Applicant: Cisco Technology, Inc.

Inventor： Chetan Narsude ,  Gaurav Gupta ,  Shadab Nazar ,  Pavan Mamillapalli ,  Sundar Iyer

IPC: H04L12/24 ,  H04L12/26 ,  G06F11/34

Abstract: Aspects of the technology provide solutions for determining a time period (“epoch”) required to monitor or analyze a tenant network. Some implementations of the technology include a process for making automatic epoch determinations, which includes steps for identifying one or more network parameters for a tenant network, analyzing the tenant network using the network parameters to discover one or more configuration settings of the tenant network, and determining a first epoch for the tenant network, the first epoch corresponding with a period of time to complete analysis of the tenant network using the network parameters. In some aspects, the process can further include steps for generating a tenant profile for the tenant network, the tenant profile based on the network parameters, the first epoch, and the one or more configuration settings of the tenant network. Systems and machine-readable media are also provided.