公开(公告)号：US09390212B2

公开(公告)日：2016-07-12

申请号：US14702971

申请日：2015-05-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC: G11C11/00 ,  G06F17/50 ,  G11C11/419

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

公开(公告)号：US20150234950A1

公开(公告)日：2015-08-20

申请号：US14702971

申请日：2015-05-04

Applicant: Cisco Technology, Inc.

Inventor： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

IPC: G06F17/50 ,  G11C11/419

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Abstract translation: 现代数字集成电路中通常需要多端口存储器电路来存储数据。 多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。 多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。 然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。 公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。