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公开(公告)号：US20210142747A1
公开(公告)日：2021-05-13
申请号：US17153120
申请日：2021-01-20
Inventor： Zhen WANG , Wenwen QIN , Mingchao MA , Wenchao HAN , Jian SUN , Yun QIAO , Jun FAN
IPC: G09G3/36
Abstract: An array substrate, a display panel, a display device, and driving methods thereof are provided. The array substrate includes subpixels arranged in an array, and switches. The subpixels include subpixels of a first color, subpixels of a second color, subpixels of a third color, subpixels of a fourth color, in odd rows of subpixels, the subpixels of the first color, the subpixels of the second color, the subpixels of the third color, the subpixels of the fourth color are sequentially arranged; in even rows of subpixels, the subpixels of the third color, the subpixels of the fourth color, the subpixels of the first color, the subpixels of the second color are sequentially arranged; and the subpixels of the first color are white subpixels; the subpixels of the second color are blue subpixels; the subpixels of the third color are green subpixels; the subpixels of the fourth color are red subpixels.
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公开(公告)号：US20200321407A1
公开(公告)日：2020-10-08
申请号：US16300642
申请日：2018-02-05
Inventor： Fuqiang TANG , Yanyan ZHAO , Zhiming LIN , Long JIN , Zhen WANG , Chun Chieh HUANG
Abstract: A display substrate, a display device and a display method thereof, and a mask plate are provided. The display substrate includes: a plurality of pixel unit groups arranged in rows, each of the pixel unit groups including: a first-color sub-pixel unit, and a ring-shaped second-color sub-pixel unit surrounding the first-color sub-pixel unit.
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公开(公告)号：US20170288142A1
公开(公告)日：2017-10-05
申请号：US15511309
申请日：2016-04-01
Inventor： Zhen WANG
CPC classification number: H01L51/0011 , G03F1/50 , G09G3/2003 , G09G3/2074 , G09G3/3208 , G09G2300/0452 , G09G2320/0233 , H01L27/3213 , H01L27/3218 , H01L51/56
Abstract: A display substrate and a fabricating method thereof, and a system for fabricating a display substrate and a display device are disclosed. The display substrate includes a plurality of pixels, each of which includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in a first direction. The fourth sub-pixel in a first pixel is adjacent to the first sub-pixel in a second pixel, and that the second pixel is adjacent to the first pixel and at a side of the first pixel in the first direction. The fourth sub-pixel in the first pixel is adjacent to the second sub-pixel in a third pixel, and the third pixel is adjacent to the first pixel and at a side of the first pixel in a second direction perpendicular to the first direction.
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公开(公告)号：US20240258335A1
公开(公告)日：2024-08-01
申请号：US18630971
申请日：2024-04-09
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136213 , G02F1/136222 , G02F1/13629 , G02F1/1368 , H01L27/1255
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; and a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); where the pattern unit (171a) further includes a second bump (1712) located within a central area surrounded by each of the first bumps (1710), and the spacing groove (1711) on a same side of the first bump (1710) and the second bump (1712) is arranged in a non-straight shape.
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公开(公告)号：US20240212772A1
公开(公告)日：2024-06-27
申请号：US17794991
申请日：2021-09-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Zhen WANG , Wenwen QIN , Han ZHANG , Deshuai WANG , Jian ZHANG , Yue SHAN , Xiaoyan YANG , Yadong ZHANG , Jian SUN
CPC classification number: G11C19/28 , G09G3/20 , G09G2310/0286
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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Patent Agency Ranking
公开(公告)号：US20230017000A1
公开(公告)日：2023-01-19
申请号：US17950131
申请日：2022-09-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhao ZHANG , Yanqing CHEN , Wei LI , Weida QIN , Kai CHEN , Jiguo WANG , Wei YAN , Xiaofeng ZHANG , Zeliang LI , Jian ZHANG , Zhen WANG
IPC: G02F1/1362 , G02F1/1335 , G02F1/13363 , G02F1/1333 , G02F1/1343 , G02F1/1341 , G06F3/041 , G06F3/044
Abstract: A display panel includes a second substrate. The second substrate includes a second base substrate and a shielding layer, an array structure layer, an insulating layer and a reflective layer which are sequentially disposed on a second base substrate, the array structure layer includes gate lines; the shielding layer includes a plurality of groups of light shielding units sequentially arranged along a first direction, each group of the light shielding units includes a plurality of independent sub-light shielding units sequentially arranged along a second direction, the reflective layer includes a plurality of reflective units arranged in an array, the plurality of reflective units form a plurality of reflective rows and a plurality of reflective columns, a first space area is formed between adjacent reflective columns, and a second space area is formed between adjacent reflective rows forms.
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公开(公告)号：US20220327987A1
公开(公告)日：2022-10-13
申请号：US17763719
申请日：2021-05-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: G09G3/20
Abstract: A display substrate, a display panel, a display apparatus, and a display driving method are provided. The display substrate includes: a display region and a peripheral region at a periphery thereof. Gate lines, data lines and a pixel array are in the display region. The pixel array includes pixel units each coupled to a corresponding gate line and data line, and color mixing pixel columns each including multiple pixel units emitting light of different colors and including periodic structures along the column direction. The number of pixel units in each periodic structure is constant. A gate driving circuit is in the peripheral region and includes cascaded shift registers each having a cascading signal output terminal and scanning signal output terminals each coupled to a corresponding gate line. The number of scanning signal output terminals of each shift register is equal to the number of pixel units in each periodic structure.
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38.发明申请公开(公告)号：US20210376057A1
公开(公告)日：2021-12-02
申请号：US16648421
申请日：2019-04-25
Inventor： Huafeng LIU , Shengwei ZHAO , Chaochao SUN , Chao WANG , Jingping LV , Lin XIE , Guoqing ZHOU , Panpan ZHANG , Tengfei WANG , Hsinghua PAN , Lele LI , Zhiqiang CHANG , Shaocong DANG , Shijie MU , Zhen WANG
Abstract: Disclosed are a display substrate, a display device, a manufacturing method and a repairing method. A capacitor structure in the display substrate includes a first electrode and a second electrode. The first electrode includes a first main body portion extending in a first direction, first branch portions extending in a second direction, and a first connection portion connecting the first branch portions to the first main body portion. The second electrode includes a second main body portion extending in the first direction, second branch portions extending in the second direction, and a second connection portion connecting the second branch portions to the second main body portion. One side of the first electrode having the first branch portions faces one side of the second electrode having the second branch portions, and each first branch portion and a corresponding second branch portion form a capacitor.
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公开(公告)号：US20210026179A1
公开(公告)日：2021-01-28
申请号：US16328562
申请日：2018-05-23
Inventor： Yun QIAO , Zhen WANG , Fei HUANG , Xiaozhou ZHAN , Han ZHANG , Wenwen QIN , Jian SUN
IPC: G02F1/1333 , G02F1/1362
Abstract: Disclosed are an array substrate, a liquid crystal display panel and a display apparatus. The array substrate comprises a plurality of pixel units, with each of which being provided with a plurality of sub-pixels (R, G, B) arranged in a first direction; a plurality of touch control electrodes, a region where each of the touch control electrodes is located overlapping with a region where the plurality of sub-pixels (R, G, B) are located; and a plurality of touch control signal lines arranged in gaps between the sub-pixels (R, G, B), wherein each of the touch control signal lines is connected to each of the touch control electrodes, there is no touch control floating signal line not connected to each of the touch control electrodes, and one column of pixel units is correspondingly provided with one touch control signal line.
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公开(公告)号：US20200051654A1
公开(公告)日：2020-02-13
申请号：US15760294
申请日：2017-09-19
Inventor： Zhen WANG , Jian SUN , Yun QIAO , Xiaozhou ZHAN , Fei HUANG , Han ZHANG , Wenwen QIN , Lele CONG , Zhengkui WANG
Abstract: The embodiments of the present disclosure relate to a shift registers unit and a driving method thereof, and a gate driving device. The shift register unit includes a first and second input circuit, a pull-down control circuit, an output circuit, a pull-down circuit, and a control circuit. The first input circuit provides a first control signal to a pull-up node. The second input circuit provides a second control signal to the pull-up node. The pull-down control circuit provides the voltage of a first voltage terminal to a pull-down node, or controls the voltage of the pull-down node. The output circuit provides a second clock signal to a signal output terminal. The pull-down circuit provides the voltage of the first voltage terminal to the pull-up node and the signal output terminal. The control circuit provides the first input signal to the pull-up node.
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