GATE DRIVING CIRCUIT, ARRAY SUBSTRATE, DISPLAY PANEL AND DRIVING METHOD

    公开(公告)号:US20180102102A1

    公开(公告)日:2018-04-12

    申请号:US15519836

    申请日:2016-08-30

    Inventor: Qiujie Su Feng Li

    Abstract: The embodiments of the present disclosure provide a gate driving circuit, an array substrate, a display panel and a driving method. The gate driving circuit comprises: at least a Gate driver on Array (GOA) unit GOAn and a GOA unit GOAn+m, an output terminal of GOAn being connected to an input terminal of GOAn+m, an output terminal of GOAn+m is connected to a reset terminal of GOAn; and an electrical leakage compensation module having two input terminals connected to output terminals of GOAn and GOAn+m, respectively, a control terminal connected to a signal line, and an output terminal connected to a Pull-Up (PU) node of GOAn+m, and configured to compensate for a voltage at the PU node of GOAn+m in response to receipt of the electrical leakage compensation signal VLHB. According to the embodiments of the present disclosure, an electrical leakage compensation module is added between two cascaded GOA units for compensating for a voltage decrease due to electrical leakage by charging the GOA unit at the next stage.

    Display panel and display device
    34.
    发明授权

    公开(公告)号:US12222619B2

    公开(公告)日:2025-02-11

    申请号:US17636148

    申请日:2021-03-10

    Abstract: A display panel and a display device are disclosed. The display panel comprises an array substrate and spacers; the array substrate comprises a first substrate, gate lines, data lines, and multiple sub-pixel units; the first substrate is provided with multiple sub-pixel regions, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions and intersecting the first wiring regions; at least part of each sub-pixel unit is located on a sub-pixel region; the gate lines and the data lines are respectively located on the first wiring regions and the second wiring regions and are electrically connected to the sub-pixel units; the data lines and the gate lines are insulated from each other and intersect each other; each data line is provided with an alignment part.

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