公开(公告)号：US11474966B2

公开(公告)日：2022-10-18

申请号：US17184507

申请日：2021-02-24

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US11275503B2

公开(公告)日：2022-03-15

申请号：US16863700

申请日：2020-04-30

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Erez Izenberg ,  Robert Michael Johnson ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Nafea Bshara ,  Christopher Joseph Pettey

IPC: G06F3/06 ,  G06F12/08 ,  G06F15/78 ,  G06F21/51 ,  G06F13/28 ,  G11C7/10

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

公开(公告)号：US11115293B2

公开(公告)日：2021-09-07

申请号：US15354765

申请日：2016-11-17

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Nafea Bshara ,  Matthew Shawn Wilson

IPC: H04L12/24 ,  G06F9/50 ,  G06F15/78

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

公开(公告)号：US10860357B1

公开(公告)日：2020-12-08

申请号：US15645624

申请日：2017-07-10

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Asif Khan ,  Nafea Bshara ,  Kiran Kalkunte Seshadri

IPC: G06F9/455 ,  G06F13/40 ,  G06F13/42

Abstract: A multi-tenant environment is described with a configurable hardware logic platform (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. The configurable hardware logic platform can be programmed with a host logic wrapper portion, which is controlled by a service provider, and a customer portion, which is programmed with logic provided by a tenant of the service provider. While the host logic wrapper portion is reprogrammed, protections are put in place to prevent a virtual machine or the customer logic from violating security built within the host logic wrapper portion. Such protections can be suspending communications between the virtual machine and the customer logic until the host logic wrapper is reprogrammed.

公开(公告)号：US20200334186A1

公开(公告)日：2020-10-22

申请号：US16918151

申请日：2020-07-01

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US20190258597A1

公开(公告)日：2019-08-22

申请号：US16287986

申请日：2019-02-27

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F15/78 ,  G06F9/445 ,  G06F13/42

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US10326651B1

公开(公告)日：2019-06-18

申请号：US15669808

申请日：2017-08-04

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta

IPC: H04L12/24 ,  G06F9/455 ,  G06F13/10 ,  G06F9/445

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating signature information with the client configurable logic for various purposes.

公开(公告)号：US09940284B1

公开(公告)日：2018-04-10

申请号：US14673474

申请日：2015-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Asif Khan ,  Thomas A. Volpe ,  Robert Michael Johnson

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4221

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

公开(公告)号：US09934065B1

公开(公告)日：2018-04-03

申请号：US15189231

申请日：2016-06-22

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson

IPC: G06F9/455 ,  G06F9/46 ,  G06F13/40

CPC classification number: G06F9/466 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/467 ,  G06F13/4068 ,  G06F2009/45579

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may have limited physical resources, such as memory. Large I/O transactions may occupy all available memory on the I/O adapter device, thus causing other I/O transactions to experience intermittent and excessive delays. The I/O adapter device can be configured to issue one or more transactions for a large I/O request. Each transaction transfers a portion of the data requested by the large I/O request. When all the transactions have completed, the client that requested the large I/O request is informed that the I/O request has completed.

公开(公告)号：US09864538B1

公开(公告)日：2018-01-09

申请号：US14750926

申请日：2015-06-25

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Mark Bradley Davis ,  Norbert Paul Kusters ,  Marc Stephen Olson ,  Marc John Brooker

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0626 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/5077

Abstract: Server computers often include one or more input/output (I/O) devices for communicating with a network or directly attached storage device. Data transferred between these devices may include blocks of data with a common often repeated and identifiable data pattern. Transfer and storage of data of this nature may be optimized by transferring primarily blocks of data that are not of the pre-determined data pattern. An indicator may be transferred and stored with transferred data that has been reduced in size in this manner.